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* Merge branch 'android-samsung-3.0-jb-mr0' of ↵Pawit Pornkitprasan2012-10-152-5/+7
|\ | | | | | | | | | | | | | | | | https://android.googlesource.com/kernel/samsung into HEAD Conflicts: drivers/gpu/pvr/pvrversion.h Change-Id: I93433944a5870a934ea7783df66994bffda2673e
| * gpu: pvr: Update to DDK 1.8@2112805Alistair Strachan2012-07-131-6/+6
| | | | | | | | | | | | | | This is a version number change only, which is required for compatibility with the user-mode driver. Change-Id: Id83c23254db8f6aac8f2f7ded8bae9040cbe5402
| * gpu: pvr: Dump active page table when lockup is detected.Alistair Strachan2012-07-091-0/+2
| |
* | aries: Use DVFS locks instead of cpufreq policy mangling in pvr.Mike Kasick2012-10-031-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pvr driver requires that the memory bus speed is kept fast while the GPU is active. Since the memory bus speed is tied to the CPU frequency, pvr (previously) used a cpufreq notifier called on policy updates to ensure the CPU is running at a minimum 200 MHz while active. The problem with this approach is that any changes to scaling_min_freq while the GPU is active (e.g., while interacting with the Processor settings menu) get clamped to 200 MHz, which persists even when the GPU is inactive. By switching to DVFS locks, changes to scaling_min_freq persist, and so allows the use of 100 MHz when the GPU is inactive. Fixes epiccm #14. Change-Id: I12bf5a6f3cba2da853d5528f4c62a659a1489806
* | Revert "aries: add OC support"Pawit Pornkitprasan2012-07-291-27/+1
| | | | | | | | | | | | | | | | | | This reverts commit 463e99c53ae3b7c18ad3bee3825d4d75c603adae See Andrew Dodd's comments on http://review.cyanogenmod.com/#/c/19820/. Also been getting rare homescreen corruption after moving PVR to DVFS lock. Change-Id: I628ca36ea63d87b6e74ef346f4acb04d5bfadeae
* | aries: add OC supportDaniel Bateman2012-07-221-1/+27
| | | | | | | | Change-Id: Iaf1e26ad7e19ea0205b7f2905f28fccc19f712f8
* | gpu: pvr: match version to driverPawit Pornkitprasan2012-07-201-1/+1
|/ | | | Change-Id: I996254dcf39b105c7f295c86bdbd3ed626e251d6
* gpu: pvr: Flush the whole CPU cache when allocating uncached.Alistair Strachan2012-06-202-0/+5
| | | | | | | This is a workaround for range-based CPU cache invalidation apparently not working reliably. Change-Id: I62fe3d10a465ee630729d7edf054f7bc82a422d8
* Revert "gpu: pvr: Add thread safety checks to SGX MMU code."jp abgrall2012-06-182-107/+2
| | | | | Not needed anymore, was just to get a prebuild that QA could use. This reverts commit ca5c535e1e9cae41831adae5a29a76f848f7f792
* Revert "gpu: pvr: Fix a bug that prevented MMU PTs from being dumped."jp abgrall2012-06-181-1/+7
| | | | | Not needed anymore, was just to get a prebuild that QA could use. This reverts commit 5a7b9539f5c1a9bb35131014907929a2da3fa723
* Revert "gpu: pvr: Harden MMU code's use-after-free checks."jp abgrall2012-06-181-31/+9
| | | | | | Not needed anymore, was just to get a prebuild that QA could use. This reverts commit d00c00ef81aba03db7d7ebcdbc0ca7c11de5d2ec
* Revert "gpu: pvr: Intentionally leak SGX MMU PTs."jp abgrall2012-06-181-5/+2
| | | | | Not needed anymore, was just to get a prebuild that QA could use. This reverts commit ce3815df4836c1f8e10f7a71213b4d2d7615c496
* gpu: pvr: Intentionally leak SGX MMU PTs.Alistair Strachan2012-06-141-2/+5
| | | | | | | | | | | | | When page tables would normally be freed, leak them instead. This experiment is to try to prove a distinction between a use-after-free type bug and another driver corrupting our page tables. At the point the asserts go off, we don't expect the page to have been freed yet. So it should contain only valid PTEs. If however the PT is being used after free, it might contain junk from other kernel drivers. If we don't free the PTs, the latter should never happen. Change-Id: I69714cfd0ee81adb9a60a996d11e8373e209dfa9
* Revert "gpu: pvr: Intentionally leak SGX MMU PTs."JP Abgrall2012-06-141-5/+2
| | | | | | | | Clicked submit in the wrong window. It needs to go after some other change. This reverts commit cc92b070b828b739cb5653407f8d22ca04762de2 Change-Id: Ie2cc8d1715af6b9c40145f5f3e857051916bea0a Signed-off-by: JP Abgrall <jpa@google.com>
* gpu: pvr: Harden MMU code's use-after-free checks.Alistair Strachan2012-06-141-9/+31
| | | | | | | | Add signature words to MMU_CONTEXT and MMU_PT_INFO. These words are initialized at alloc time and zeroed at free time. They are checked any time a page table is validated before being freed. Change-Id: I74aa57c1e8b48e89bfbb1f4f8a4120c54859122f
* gpu: pvr: Intentionally leak SGX MMU PTs.Alistair Strachan2012-06-141-2/+5
| | | | | | | | | | | | | When page tables would normally be freed, leak them instead. This experiment is to try to prove a distinction between a use-after-free type bug and another driver corrupting our page tables. At the point the asserts go off, we don't expect the page to have been freed yet. So it should contain only valid PTEs. If however the PT is being used after free, it might contain junk from other kernel drivers. If we don't free the PTs, the latter should never happen. Change-Id: I3046bb81896ed6ae4ea1f2de19a62a0e5e89e063
* gpu: pvr: Fix a bug that prevented MMU PTs from being dumped.Alistair Strachan2012-06-141-7/+1
| | | | | | | | | | | DumpPT already had a static inline if PT_DEBUG or PT_DUMP weren't defined, so it shouldn't have been #ifdef guarded. Furthermore, PT_DEBUG isn't enabled so DumpPT would not have been called to dump the page tables in one case. This is incorrect as it should have been called if PT_DUMP was enabled. Change-Id: I4a0d2a3665b7586a5dfa4390098df4edb6edfe74
* gpu: pvr: Add thread safety checks to SGX MMU code.Alistair Strachan2012-06-142-2/+107
| | | | | | | | | | | | | | | | The SGX MMU code was not designed to be used from multiple driver threads. One theory is that somehow the driver does sometimes use the MMU code from multiple threads, which could cause corruption of meta data. We must allow PID 1 through because the kernel uses this ID before userspace is up, and the module_init code interacts with the MMU subsystem. Otherwise, check that the outer bridge lock is held. If it is held, check the PID of the caller matches the PID holding the bridge lock. Change-Id: I35f42f251316b158576e5d853f8099e24942b4f2
* gpu: pvr: Update to DDK 1.8@945322Alistair Strachan2012-06-061-3/+3
| | | | | | | This is a version number change only, for compatibility with the user-mode driver. Change-Id: I272428a490fbbd18ce9016e92e82829c5dc6b898
* Revert "gpu: pvr: Update to DDK 1.8@943950"JP Abgrall2012-06-051-3/+3
| | | | | | | This reverts commit a4f4aa198065e8d33f86cf3567bb4aba0eac5eef. The DDK change is not yet qualified as a JB release. But there is a USB VBUS fix needed.
* gpu: pvr: Update to DDK 1.8@943950Ben Jones2012-06-011-3/+3
| | | | | | | This is a version number change only, for compatibility with the user-mode driver. Change-Id: I0cfc6d73c1a386597f96efa97a3bd2e2d366e760
* gpu: pvr: Update to DDK 1.8@905891Ben Jones2012-05-142-57/+80
| | | | | | - Fix some bugs in the newly introduced memory pool code (b/6096575) Change-Id: Ib505041f98ffedf9ae785c79d49ce719202cacb0
* gpu: pvr: Update to DDK 1.8@904153Alistair Strachan2012-05-1413-458/+1213
| | | | | | | | | | | - Fix http://b/6446135 "eglHibernateProcessIMG slows down.." Release the bridge mutex in various places while waiting on the hardware. Permits multiple userspace processes/threads entering the driver simulataneously in some controlled cases. - Fix http://b/6096575 "some gralloc operations are very slow" Add a shrinkable pool for uncached memory allocations. Change-Id: I5a2554b351e10b3b35aaccc0ae943a78c1af673c
* gpu: pvr: Update to DDK 1.8@901807Alistair Strachan2012-05-021-2/+2
| | | | Change-Id: Iee12a4cbba24269b0a6901324ee2e07b5119a063
* gpu: pvr: Update to DDK 1.8@900138.Alistair Strachan2012-05-0114-69/+218
| | | | | | | | - Fixed "XPROC workaround in a bad state" messages, issue http://b/5806132. - Fixed missing GPL header in sgx_ukernel_status_codes.h. Change-Id: Id7c73b4367f4534b44e2170c4610803050c7b396
* gpu: pvr: Update to DDK 1.8@873556Alistair Strachan2012-04-189-50/+993
| | | | | | | | | | - Allow SGX compositions requiring implicit synchronization to correctly synchronize with more than 8 buffers. This feature has been tested with 16 buffers. - Enable kernel driver to decode SGX firmware status codes. Fixes http://b/6168368 Change-Id: Ie2d9cc4f739f28aaead8c2c2b85609456b4b2072
* gpu: pvr: Re-enable MMU pagetable write-protectionBen Jones2012-04-051-0/+1
| | | | This reverts commit b43c0161fbca901e586e9ade321a5d8e616f94b9.
* gpu: pvr: Update to DDK 1.8@869593Ben Jones2012-04-0419-130/+239
| | | | | | | | | | - Fix a bug in the PVRSRV_MMU_MAKE_READWRITE_ON_DEMAND feature (b/6195660) which caused an assert to go off when the driver attempted to make GPU pagetable memory read-write. - Add missing PVRSRVKernelSyncInfoDecRef calls to error paths. Change-Id: I21dace59073a38221d838ec74fa70eea92a6a2b4
* Revert "gpu: pvr: Switch on MMU pagetable write-protection."JP Abgrall2012-03-211-1/+0
| | | | | | | | | This reverts commit b8f7c03589e2d0f0b98a56c80c4ee0f42ad40df8 Imgtec now have collected enough info to fix their bug. Change-Id: I0576665064ffad3473d3716c37208032278d246d Signed-off-by: JP Abgrall <jpa@google.com>
* gpu: pvr: Update to DDK 1.8@840215Alistair Strachan2012-03-142-4/+16
| | | | Change-Id: I899b6a4ed9e88a0e5c4c2e426aee4e11de846a14
* gpu: pvr: Switch on MMU pagetable write-protection.Alistair Strachan2012-03-141-0/+1
| | | | | | | | Make the SGX MMU page tables read-only when the SGX driver has finished writing them. Should catch other drivers writing to the page-table memory when they do not own it. Change-Id: I49800be0188878f7992d0a4d72360761c6c74007
* gpu: pvr: Update to DDK 1.8@813213Alistair Strachan2012-03-143-12/+175
| | | | | | | | - Add PVRSRV_MMU_MAKE_READWRITE_ON_DEMAND feature for Crespo MapPage() crash bug investigation. This will write-protect the MMU pagetables when the SGX driver is not modifying them. Change-Id: I450ead2b020d42dde14522b46c06f63eb75ff6b5
* gpu: pvr: Update to DDK 1.8@808799Alistair Strachan2012-03-145-15/+56
| | | | | | | - Fix a bad pointer dereference in services DC. - Correct GPL license text in two files. Change-Id: I0eacdabd5f690969a372bdd88b8d0e7bc2b775ff
* gpu: pvr: Update to DDK 1.8@796887.Alistair Strachan2012-03-147-7/+78
| | | | | | | | | - Re-introduce DC refcounting fix, which makes an unrelated (and unfixed) problem more reproducible. - Fix a bug where the driver would not wait for propagation (during power transitions) before performing a soft reset. Change-Id: I192e23f652dc01eb5f08a0abd48e156564fd0bb5
* gpu: pvr: Update to DDK 1.8@795947Alistair Strachan2012-03-141-2/+2
| | | | Change-Id: I62fe8e0f0c5f4046a4852d8dfb92c8b0991df378
* gpu: pvr: Update to DDK 1.8@794370Alistair Strachan2012-03-1420-214/+764
| | | | Change-Id: I403eb902947b552d5b17260e05b8d5543d99c977
* gpu: pvr: Update to DDK 1.8@785978Alistair Strachan2011-12-088-25/+166
| | | | | | | - Revert 1.8@778707 bugfix to queue.c (again). - Merge up refcount debugging changes (can still be compiled out). Change-Id: I59faeba3211b20566ec846528ae9f68c51181b67
* gpu: pvr: Update to DDK 1.8@782952Alistair Strachan2011-11-3014-56/+663
| | | | | | | | | - Add reference count debugging feature to dump out the last 256 object reference count modifications. - Flush the CPU cache before 3D transfers or 2D core operations. Fixes glCopyTexSubImage2D() of SW-rendered EGLImage. Change-Id: I86cfb0623acad8f20c381eefacdece6fba738ea5
* gpu: pvr: Update to DDK 1.8@780962Ben Jones2011-11-231-2/+2
| | | | | This is a version number change only, which is required for compatibility with the user-mode driver.
* gpu: pvr: Update to DDK 1.8@780209Alistair Strachan2011-11-214-19/+5
| | | | | | | This is a version number change only, which is required for compatibility with the user-mode driver. Change-Id: I24ee92b9cc7800c7e52e20ce0e24ac5dbba7110e
* gpu: pvr: Update to DDK 1.8@779532Alistair Strachan2011-11-171-4/+4
| | | | | | | This is a version number change only, which is required for compatibility with the user-mode driver. Change-Id: I8529046b7f78cd99fdb458afca37d96d84b686c8
* gpu: pvr: Update to DDK 1.8@779202Alistair Strachan2011-11-1710-19/+99
| | | | | | | - Dump SGX page tables if corruption is detected. - Fix a security issue found in various PVR ioctls Change-Id: Ic62f4671ab66b7be53a913e5023eb79342e223db
* gpu: pvr: Update to DDK 1.8@550175Alistair Strachan2011-11-179-124/+55
| | | | | | | | | | | | | | - Remove ProcessFlipV2 as Samsung SLSI implemented their own HWC that does not integrate with the GPU driver. This code has never been used in production. - Merge in DC interface cleanups from Prime. Does not affect Crespo because ProcessFlipV2 has been removed. - SGXDumpDebugInfo() changes to help progress various bug investigations. Change-Id: I0d48253bfb7c17fea0795b63e48b2e026111dd2c
* s5p: gpu: pvr: tweak cpufreq policy min freq if GPU is busyJP Abgrall2011-11-171-0/+39
| | | | | | | | | | On s5pv210 the cpufreq lower frequencies affect the memory bus which in turn affects the GPU when it is actually busy. To avoid cpufreq impacting the GPU when it is busy, the GPU now tweaks the policy's min freq based on its activity. Change-Id: I2a48726d7f1d783be47b39fc904ad5411cc390b0 Signed-off-by: JP Abgrall <jpa@google.com>
* gpu: pvr: Temporarily disable PVRSRV_RESET_ON_HWTIMEOUT.Alistair Strachan2011-11-171-1/+0
| | | | | Disable this to get firmware traces to investigate various crespo lockups.
* gpu: pvr: Update to DDK 1.6.16.4046Alistair Strachan2011-11-17140-3240/+12095
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change-Id: If38412971f275715a47bf200aeebe1139d2620f8 gpu: pvr: Update DDK version number to 1.6.16.4061 This is a version number change only, which is required for compatibility with the user-mode driver. Change-Id: I4e0f59a8f98ea28f9c0862aff76c0bfa2710efe0 gpu: pvr: Update to DDK 1.6.16.4124 Change-Id: Ifbc47f2552f031e92e02b31a9715e3e42cf14b3c gpu: pvr: Update DDK version number to 1.6.16.4131 This is a version number change only, which is required for compatibility with the user-mode driver. Change-Id: I8c4df3ae638ad2d358aa3977ffb7f6e9bdb1de4a gpu: pvr: Update to DDK 1.7.17.4142 Signed-off-by: Simon Wilson <simonwilson@google.com> gpu: pvr: Update to DDK 1.7.17.4474 Signed-off-by: Simon Wilson <simonwilson@google.com> gpu: pvr: Update to DDK 1.8.18.380 gpu: pvr: Update to DDK 1.8.18.468 gpu: pvr: Update to DDK 1.8.18.684 Change-Id: I7a4e92add9f1c61862a06e51b68169d93b67a001 Signed-off-by: JP Abgrall <jpa@google.com> gpu: pvr: Update to DDK 1.8.18.726 gpu: pvr: Update to DDK 1.8.18.749 gpu: pvr: Fix to compile on 2.6.39 Change-Id: I79c07b3a0ca219f7e6d8dec97f41adc3fc5a01ff Signed-off-by: Arve Hjønnevåg <arve@android.com> gpu: pvr: Update to DDK 1.8.18.834 Fix a couple of double frees in PVRSRVSwapToDCBuffer2KM. Fixes for various ION client refcounting issues. gpu: pvr: Update to DDK 1.8.18.844 Various fixes to prevent arbitrary memory corruption with ION: * Remove the per-process ION client - there is now just one "kernel" ION client * Ensure that the mmap mutex is taken before walking the offset struct list * Implement ION cache flush code gpu: pvr: Update to DDK 1.8.18.853 Change-Id: I5e2e1619aae0634ca5036c5ab60e1e4339a35b0d gpu: pvr: Update to DDK 1.8.18.866 Change-Id: I91548bf62aa30ff41814118a3a6d49303fc16bfc gpu: pvr: Update to DDK 1.8.18.877 Change-Id: Id87c6318a7705ad51e5bfd487a9b216f373c0caf gpu: pvr: Update to DDK 1.8.18.891 This is a version number change only, which is required for compatibility with the user-mode driver. Change-Id: I30b11a79973179d7dcb0923d2106a1f072b88a77 gpu: pvr: Update to DDK 1.8.18.919 - Bump CONFIG_FB_S3C_NR_BUFFERS to 6, to increase the display carveout size by 3MB. This is to make space for video-decode buffers. - drivers/gpu/pvr Makefile cleanups. Remove dead build options. - Groundwork for "multiple readers" capability required by HWC. - Merge s3c_lcd and s5pc110 display and system code with latest versions. Add video-decode carveout capability. Change-Id: I8836204451eebf12b030404177cfd6bc4b294489 gpu: pvr: Update to DDK 1.8.18.927 - More work on "multiple reader" capability for HWC. Change-Id: I0fd372b03de5bb86591d4b2be208be3749670248 gpu: pvr: Update to DDK 1.8.18.943 Change-Id: Iae3d13fc82dfa0cffc6bce98a056f1b0d4b1f62a gpu: pvr: Update to DDK 1.8.18.945 - Add ProcessFlip V2 capability to s3c_displayclass.c. - Enables FIMC integration. Change-Id: Ibc1dec9c24f5f55ce1436674b36571f3718b4e96 gpu: pvr: Update to DDK 1.8.18.964 - Add SUPPORT_GET_DC_BUFFERS_SYS_PHYADDRS to enable returning of display buffer physical addresses to user-space. Required for C110 HWC. Not enabled on Prime. Change-Id: I5f19c7b1cea193aaca24cceca518d0100171c823 gpu: pvr: Update to DDK 1.8@273945 This is a version number change only, which is required for compatibility with the user-mode driver. gpu: pvr: Update to DDK 1.8@274226 gpu: pvr: Update to DDK 1.8@274836 gpu: pvr: Update to DDK 1.8@275425 This is a version number change only, which is required for compatibility with the user-mode driver. gpu: pvr: Update to DDK 1.8@275540 - Allow userspace to obtain a copy of the current kernel reference count of a MemInfo. Fixes a bug on crespo that allowed a Y/UV swapchain buffer to be incorrectly re-used in another allocation. Change-Id: I6a10d75ad9efb4109b6bfa34b3478dc7b36caac2 gpu: pvr: Update to DDK 1.8@275916 gpu: pvr: Update to DDK 1.8@276629 Merged with upstream s3c_lcd. gpu: pvr: Update to DDK 1.8@278427 - Fix a possible livelock scenario in s3c_lcd, by scheduling the MISR in the vsync handler. Change-Id: If5c57b8a8658159d2912d89074015bb03b3f5ed3 gpu: pvr: Update to DDK 1.8@279068 Also make it possible to build the debug (pdump) driver. Change-Id: I90f9a5c566a9d6205e801302bfb4f881f53e3247 gpu: pvr: Update to DDK 1.8@288777 This is a version number change only, which is required for compatibility with the user-mode driver. Change-Id: Ia22454fd91e280cf35cf798806dfa2b9505d0018 gpu: pvr: Update to DDK 1.8@289037 - Merge with upstream TILER allocation wrap support in preparation for video encoder integration. - Suppress some overly verbose kernel messages. - Remove incorrect/unnecssary VM_PFNMAP sanity check. Change-Id: Ia30a3316e1c9d2dc421afa5068a977b25618c85d gpu: pvr: Update to DDK 1.8@289270 This is a version number change only, which is required for compatibility with the user-mode driver. Change-Id: Ic827cd7f22792c900708e77b0af48d5824790581 gpu: pvr: Update to DDK 1.8@289794 This is a version number change only, which is required for compatibility with the user-mode driver. Change-Id: Iba07b4cb193d87000aacb0408993841b99c8cb3e gpu: pvr: Update to DDK 1.8@291121 - Merged TI heap configuration change - Pass ROC2 devvaddr through to userspace (better debug) Change-Id: Ie43b9af490190adbe0d1e34119af392f1ea420f5 gpu: pvr: Update to DDK 1.8@292125 Change-Id: I2b6e31f950a7ea98ff4db4feb160886c3d6eab7c gpu: pvr: Update to DDK 1.8@292423 Change-Id: I4086ba1f3f3a6e5f7e605b156d1e01151da17223 gpu: pvr: Update to DDK 1.8@293295 Change-Id: Iec7d62292583d6b8e0fa157aa32e3156090a529d gpu: pvr: Update to DDK 1.8@295945 - Make sure buffer IDs propagate to other process mappings. Debug feature only. Change-Id: Id4b360b9e6b76951129791200d1df7e8d42708e9 gpu: pvr: Update to DDK 1.8@297401 - Security fixes. Remove ability to map primary surface in any process. Hide user-accessible path to OSPanic(). Change-Id: Iff7d56b04400625cac6f1f6e123749bdaeb3908c gpu: pvr: Update to DDK 1.8@298138 This is a version number change only, which is required for compatibility with the user-mode driver. Change-Id: I9edf13aaedf0b56c9922c63d84a2d99ec7b6aae3 gpu: pvr: Update to DDK 1.8@300406 This is a version number change only, which is required for compatibility with the user-mode driver. Change-Id: I6cde977c5cfdf13f7ef43e01f2c0dba1bc0659b6
* s3c_lcd: allow a different swap chain lengthAlistair Strachan2011-11-171-2/+2
| | | | | | | Allow the swap chain length to be different to the number of available swap buffers. Signed-off-by: Simon Wilson <simonwilson@google.com>
* S5PC11X: PVR: Fix PVR lockup caused by S3C_VSYNC_FLIP_ITEM access.hoony.yu2011-11-171-36/+57
| | | | | | | | - expanding work queue to whole vsync intr hander to avoid corruption in isr and suspend function. Change-Id: I30514bfc81fab959723a4d51dd2b50e793520ba4 Signed-off-by: Kisoo Yu <ksoo.yu@samsung.com>
* S5PC11X: PVR: Add power domain control code using regulator API.huisung.kang2011-11-172-29/+27
| | | | | Change-Id: I89ff99d18181b0d85c33443f9dba4f34a9741dbc Signed-off-by: huisung.kang <hs1218.kang@samsung.com>
* gpu: pvr: Only service pending CPU cache ops before LASTKICK TAs.Alistair Strachan2011-11-177-27/+38
| | | | Change-Id: I62d59e844347b93ab995aecfa0d5566879b9d87c
generated by cgit v1.1 at 2025-08-16 00:23:53 +0000