1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
|
#ifndef _ASM_NATIVE_PVCHK_INST_H
#define _ASM_NATIVE_PVCHK_INST_H
/******************************************************************************
* arch/ia64/include/asm/native/pvchk_inst.h
* Checker for paravirtualizations of privileged operations.
*
* Copyright (C) 2005 Hewlett-Packard Co
* Dan Magenheimer <dan.magenheimer@hp.com>
*
* Copyright (c) 2008 Isaku Yamahata <yamahata at valinux co jp>
* VA Linux Systems Japan K.K.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
/**********************************************
* Instructions paravirtualized for correctness
**********************************************/
/* "fc" and "thash" are privilege-sensitive instructions, meaning they
* may have different semantics depending on whether they are executed
* at PL0 vs PL!=0. When paravirtualized, these instructions mustn't
* be allowed to execute directly, lest incorrect semantics result.
*/
#define fc .error "fc should not be used directly."
#define thash .error "thash should not be used directly."
/* Note that "ttag" and "cover" are also privilege-sensitive; "ttag"
* is not currently used (though it may be in a long-format VHPT system!)
* and the semantics of cover only change if psr.ic is off which is very
* rare (and currently non-existent outside of assembly code
*/
#define ttag .error "ttag should not be used directly."
#define cover .error "cover should not be used directly."
/* There are also privilege-sensitive registers. These registers are
* readable at any privilege level but only writable at PL0.
*/
#define cpuid .error "cpuid should not be used directly."
#define pmd .error "pmd should not be used directly."
/*
* mov ar.eflag =
* mov = ar.eflag
*/
/**********************************************
* Instructions paravirtualized for performance
**********************************************/
/*
* Those instructions include '.' which can't be handled by cpp.
* or can't be handled by cpp easily.
* They are handled by sed instead of cpp.
*/
/* for .S
* itc.i
* itc.d
*
* bsw.0
* bsw.1
*
* ssm psr.ic | PSR_DEFAULT_BITS
* ssm psr.ic
* rsm psr.ic
* ssm psr.i
* rsm psr.i
* rsm psr.i | psr.ic
* rsm psr.dt
* ssm psr.dt
*
* mov = cr.ifa
* mov = cr.itir
* mov = cr.isr
* mov = cr.iha
* mov = cr.ipsr
* mov = cr.iim
* mov = cr.iip
* mov = cr.ivr
* mov = psr
*
* mov cr.ifa =
* mov cr.itir =
* mov cr.iha =
* mov cr.ipsr =
* mov cr.ifs =
* mov cr.iip =
* mov cr.kr =
*/
/* for intrinsics
* ssm psr.i
* rsm psr.i
* mov = psr
* mov = ivr
* mov = tpr
* mov cr.itm =
* mov eoi =
* mov rr[] =
* mov = rr[]
* mov = kr
* mov kr =
* ptc.ga
*/
/*************************************************************
* define paravirtualized instrcution macros as nop to ingore.
* and check whether arguments are appropriate.
*************************************************************/
/* check whether reg is a regular register */
.macro is_rreg_in reg
.ifc "\reg", "r0"
nop 0
.exitm
.endif
;;
mov \reg = r0
;;
.endm
#define IS_RREG_IN(reg) is_rreg_in reg ;
#define IS_RREG_OUT(reg) \
;; \
mov reg = r0 \
;;
#define IS_RREG_CLOB(reg) IS_RREG_OUT(reg)
/* check whether pred is a predicate register */
#define IS_PRED_IN(pred) \
;; \
(pred) nop 0 \
;;
#define IS_PRED_OUT(pred) \
;; \
cmp.eq pred, p0 = r0, r0 \
;;
#define IS_PRED_CLOB(pred) IS_PRED_OUT(pred)
#define DO_SAVE_MIN(__COVER, SAVE_IFS, EXTRA, WORKAROUND) \
nop 0
#define MOV_FROM_IFA(reg) \
IS_RREG_OUT(reg)
#define MOV_FROM_ITIR(reg) \
IS_RREG_OUT(reg)
#define MOV_FROM_ISR(reg) \
IS_RREG_OUT(reg)
#define MOV_FROM_IHA(reg) \
IS_RREG_OUT(reg)
#define MOV_FROM_IPSR(pred, reg) \
IS_PRED_IN(pred) \
IS_RREG_OUT(reg)
#define MOV_FROM_IIM(reg) \
IS_RREG_OUT(reg)
#define MOV_FROM_IIP(reg) \
IS_RREG_OUT(reg)
#define MOV_FROM_IVR(reg, clob) \
IS_RREG_OUT(reg) \
IS_RREG_CLOB(clob)
#define MOV_FROM_PSR(pred, reg, clob) \
IS_PRED_IN(pred) \
IS_RREG_OUT(reg) \
IS_RREG_CLOB(clob)
#define MOV_TO_IFA(reg, clob) \
IS_RREG_IN(reg) \
IS_RREG_CLOB(clob)
#define MOV_TO_ITIR(pred, reg, clob) \
IS_PRED_IN(pred) \
IS_RREG_IN(reg) \
IS_RREG_CLOB(clob)
#define MOV_TO_IHA(pred, reg, clob) \
IS_PRED_IN(pred) \
IS_RREG_IN(reg) \
IS_RREG_CLOB(clob)
#define MOV_TO_IPSR(pred, reg, clob) \
IS_PRED_IN(pred) \
IS_RREG_IN(reg) \
IS_RREG_CLOB(clob)
#define MOV_TO_IFS(pred, reg, clob) \
IS_PRED_IN(pred) \
IS_RREG_IN(reg) \
IS_RREG_CLOB(clob)
#define MOV_TO_IIP(reg, clob) \
IS_RREG_IN(reg) \
IS_RREG_CLOB(clob)
#define MOV_TO_KR(kr, reg, clob0, clob1) \
IS_RREG_IN(reg) \
IS_RREG_CLOB(clob0) \
IS_RREG_CLOB(clob1)
#define ITC_I(pred, reg, clob) \
IS_PRED_IN(pred) \
IS_RREG_IN(reg) \
IS_RREG_CLOB(clob)
#define ITC_D(pred, reg, clob) \
IS_PRED_IN(pred) \
IS_RREG_IN(reg) \
IS_RREG_CLOB(clob)
#define ITC_I_AND_D(pred_i, pred_d, reg, clob) \
IS_PRED_IN(pred_i) \
IS_PRED_IN(pred_d) \
IS_RREG_IN(reg) \
IS_RREG_CLOB(clob)
#define THASH(pred, reg0, reg1, clob) \
IS_PRED_IN(pred) \
IS_RREG_OUT(reg0) \
IS_RREG_IN(reg1) \
IS_RREG_CLOB(clob)
#define SSM_PSR_IC_AND_DEFAULT_BITS_AND_SRLZ_I(clob0, clob1) \
IS_RREG_CLOB(clob0) \
IS_RREG_CLOB(clob1)
#define SSM_PSR_IC_AND_SRLZ_D(clob0, clob1) \
IS_RREG_CLOB(clob0) \
IS_RREG_CLOB(clob1)
#define RSM_PSR_IC(clob) \
IS_RREG_CLOB(clob)
#define SSM_PSR_I(pred, pred_clob, clob) \
IS_PRED_IN(pred) \
IS_PRED_CLOB(pred_clob) \
IS_RREG_CLOB(clob)
#define RSM_PSR_I(pred, clob0, clob1) \
IS_PRED_IN(pred) \
IS_RREG_CLOB(clob0) \
IS_RREG_CLOB(clob1)
#define RSM_PSR_I_IC(clob0, clob1, clob2) \
IS_RREG_CLOB(clob0) \
IS_RREG_CLOB(clob1) \
IS_RREG_CLOB(clob2)
#define RSM_PSR_DT \
nop 0
#define SSM_PSR_DT_AND_SRLZ_I \
nop 0
#define BSW_0(clob0, clob1, clob2) \
IS_RREG_CLOB(clob0) \
IS_RREG_CLOB(clob1) \
IS_RREG_CLOB(clob2)
#define BSW_1(clob0, clob1) \
IS_RREG_CLOB(clob0) \
IS_RREG_CLOB(clob1)
#define COVER \
nop 0
#define RFI \
br.ret.sptk.many rp /* defining nop causes dependency error */
#endif /* _ASM_NATIVE_PVCHK_INST_H */
|
