S5PC110: GPIOLIB: Cleanup codes related to gpiolib

This patch cleanup codes in arch/arm/mach-s5pv210/gpiolib.c
We observe linux coding standard rules using 'checkpatch.pl'

1 files changed, 114 insertions, 128 deletions

diff --git a/drivers/gpio/gpio-s5pv210.c b/drivers/gpio/gpio-s5pv210.c
index 834fe62..f4226a2 100644
--- a/drivers/gpio/gpio-s5pv210.c
+++ b/drivers/gpio/gpio-s5pv210.c
@@ -435,187 +435,173 @@ static struct s3c_gpio_chip s5pv210_gpio_4bit[] = {
 /* S5PV210 machine dependent GPIO help function */
 int s3c_gpio_slp_cfgpin(unsigned int pin, unsigned int config)
 {
-        struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
-        void __iomem *reg;
-        unsigned long flags;
-        int offset;
-        u32 con;
-        int shift;
+	struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
+	void __iomem *reg;
+	unsigned long flags;
+	int offset;
+	u32 con;
+	int shift;
 
-        if (!chip)
-                return -EINVAL;
+	if (!chip)
+		return -EINVAL;
 
-	if((pin <= S5PV210_GPH3(7)) && (pin >= S5PV210_GPH0(0))) {
-                return -EINVAL;
-        }
+	if ((pin <= S5PV210_GPH3(7)) && (pin >= S5PV210_GPH0(0)))
+		return -EINVAL;
 
-        if(config > S3C_GPIO_SLP_PREV)
-        {
-                 return -EINVAL;
-        }
+	if (config > S3C_GPIO_SLP_PREV)
+		return -EINVAL;
 
-        reg = chip->base + 0x10;
+	reg = chip->base + 0x10;
 
-        offset = pin - chip->chip.base;
-        shift = offset * 2;
+	offset = pin - chip->chip.base;
+	shift = offset * 2;
 
-        local_irq_save(flags);
+	local_irq_save(flags);
 
-        con = __raw_readl(reg);
-        con &= ~(3 << shift);
-        con |= config << shift;
-         __raw_writel(con, reg);
+	con = __raw_readl(reg);
+	con &= ~(3 << shift);
+	con |= config << shift;
+	__raw_writel(con, reg);
 
-        local_irq_restore(flags);
-        return 0;
+	local_irq_restore(flags);
+	return 0;
 }
 
-
 s3c_gpio_pull_t s3c_gpio_get_slp_cfgpin(unsigned int pin)
 {
-        struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
-        void __iomem *reg;
-        unsigned long flags;
-        int offset;
-        u32 con;
-        int shift;
+	struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
+	void __iomem *reg;
+	unsigned long flags;
+	int offset;
+	u32 con;
+	int shift;
 
-        if (!chip)
-                return -EINVAL;
+	if (!chip)
+		return -EINVAL;
 
-	if((pin <= S5PV210_GPH3(7)) && (pin >= S5PV210_GPH0(0))) {
-                return -EINVAL;
-        }
+	if ((pin <= S5PV210_GPH3(7)) && (pin >= S5PV210_GPH0(0)))
+		return -EINVAL;
 
-        reg = chip->base + 0x10;
+	reg = chip->base + 0x10;
 
-        offset = pin - chip->chip.base;
-        shift = offset * 2;
+	offset = pin - chip->chip.base;
+	shift = offset * 2;
 
-        local_irq_save(flags);
+	local_irq_save(flags);
 
-        con = __raw_readl(reg);
-        con >>= shift;
-        con &= 0x3;
+	con = __raw_readl(reg);
+	con >>= shift;
+	con &= 0x3;
 
-        local_irq_restore(flags);
+	local_irq_restore(flags);
 
-        return (__force s3c_gpio_pull_t)con;
+	return (__force s3c_gpio_pull_t)con;
 }
 
-
 int s3c_gpio_slp_setpull_updown(unsigned int pin, unsigned int config)
 {
-        struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
-        void __iomem *reg;
-        unsigned long flags;
-        int offset;
-        u32 con;
-        int shift;
-
-        if (!chip)
-                return -EINVAL;
-
-	if((pin <= S5PV210_GPH3(7)) && (pin >= S5PV210_GPH0(0))) {
-                return -EINVAL;
-        }
-
-        if(config > S3C_GPIO_PULL_UP)
-        {
-                return -EINVAL;
-        }
-        reg = chip->base + 0x14;
-
-        offset = pin - chip->chip.base;
-        shift = offset * 2;
-
-        local_irq_save(flags);
-
-        con = __raw_readl(reg);
-        con &= ~(3 << shift);
-        con |= config << shift;
-        __raw_writel(con, reg);
-
-        local_irq_restore(flags);
-                           
+	struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
+	void __iomem *reg;
+	unsigned long flags;
+	int offset;
+	u32 con;
+	int shift;
+
+	if (!chip)
+		return -EINVAL;
+
+	if ((pin <= S5PV210_GPH3(7)) && (pin >= S5PV210_GPH0(0)))
+		return -EINVAL;
+
+	if (config > S3C_GPIO_PULL_UP)
+		return -EINVAL;
+	reg = chip->base + 0x14;
+
+	offset = pin - chip->chip.base;
+	shift = offset * 2;
+
+	local_irq_save(flags);
+
+	con = __raw_readl(reg);
+	con &= ~(3 << shift);
+	con |= config << shift;
+	__raw_writel(con, reg);
+
+	local_irq_restore(flags);
+
 	return 0;
 }
 EXPORT_SYMBOL(s3c_gpio_slp_setpull_updown);
 
-
 int s3c_gpio_set_drvstrength(unsigned int pin, unsigned int config)
 {
-        struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
-        void __iomem *reg;
-        unsigned long flags;
-        int offset;
-        u32 con;
-        int shift;
+	struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
+	void __iomem *reg;
+	unsigned long flags;
+	int offset;
+	u32 con;
+	int shift;
 
-        if (!chip)
-                return -EINVAL;
+	if (!chip)
+		return -EINVAL;
 
-        if(config  > S3C_GPIO_DRVSTR_4X)
-        {
-                return -EINVAL;
-        }
+	if (config  > S3C_GPIO_DRVSTR_4X)
+		return -EINVAL;
 
-        reg = chip->base + 0x0c;
+	reg = chip->base + 0x0c;
 
-        offset = pin - chip->chip.base;
-        shift = offset * 2; 
+	offset = pin - chip->chip.base;
+	shift = offset * 2;
 
-        local_irq_save(flags);
+	local_irq_save(flags);
 
-        con = __raw_readl(reg);
-        con &= ~(3 << shift);
-        con |= config << shift;
+	con = __raw_readl(reg);
+	con &= ~(3 << shift);
+	con |= config << shift;
 
-        __raw_writel(con, reg);
-#ifdef  S5PC11X_ALIVEGPIO_STORE
-        con = __raw_readl(reg);
+	__raw_writel(con, reg);
+#ifdef S5PC11X_ALIVEGPIO_STORE
+	con = __raw_readl(reg);
 #endif
 
-        local_irq_restore(flags);
-                           
+	local_irq_restore(flags);
+
 	return 0;
 }
 
 int s3c_gpio_set_slewrate(unsigned int pin, unsigned int config)
 {
-        struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
-        void __iomem *reg;
-        unsigned long flags;
-        int offset;
-        u32 con;
-        int shift;
+	struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
+	void __iomem *reg;
+	unsigned long flags;
+	int offset;
+	u32 con;
+	int shift;
 
-        if (!chip)
-                return -EINVAL;
+	if (!chip)
+		return -EINVAL;
 
-        if(config > S3C_GPIO_SLEWRATE_SLOW)
-        {
-                return -EINVAL;
-        }
+	if (config > S3C_GPIO_SLEWRATE_SLOW)
+		return -EINVAL;
 
-        reg = chip->base + 0x0c;
+	reg = chip->base + 0x0c;
 
-        offset = pin - chip->chip.base;
-        shift = offset; 
+	offset = pin - chip->chip.base;
+	shift = offset;
 
-        local_irq_save(flags);
+	local_irq_save(flags);
 
-        con = __raw_readl(reg);
-        con &= ~(1<< shift);
-        con |= config << shift;
+	con = __raw_readl(reg);
+	con &= ~(1 << shift);
+	con |= config << shift;
 
-        __raw_writel(con, reg);
-#ifdef  S5PC11X_ALIVEGPIO_STORE
-        con = __raw_readl(reg);
+	__raw_writel(con, reg);
+#ifdef S5PC11X_ALIVEGPIO_STORE
+	con = __raw_readl(reg);
 #endif
 
-        local_irq_restore(flags);
-                           
+	local_irq_restore(flags);
+
 	return 0;
 }