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| author | Joe Perches <joe@perches.com> | 2008-02-03 16:57:20 +0200 |
|---|---|---|
| committer | Adrian Bunk <bunk@kernel.org> | 2008-02-03 16:57:20 +0200 |
| commit | eebfa976ad35b1a0debd359f1c4daed3856e21f8 (patch) | |
| tree | 61a0c6c4ff7185c0d81cbcf5ae24770cca1ee9b7 | |
| parent | 603e82edf78ad6c0f836023f8db585620211947b (diff) | |
| download | kernel_samsung_crespo-eebfa976ad35b1a0debd359f1c4daed3856e21f8.zip kernel_samsung_crespo-eebfa976ad35b1a0debd359f1c4daed3856e21f8.tar.gz kernel_samsung_crespo-eebfa976ad35b1a0debd359f1c4daed3856e21f8.tar.bz2 | |
include/asm-mips/: Spelling fixes
Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: Adrian Bunk <bunk@kernel.org>
| -rw-r--r-- | include/asm-mips/mach-excite/excite_fpga.h | 2 | ||||
| -rw-r--r-- | include/asm-mips/mach-wrppmc/mach-gt64120.h | 2 | ||||
| -rw-r--r-- | include/asm-mips/sgi/ip22.h | 2 | ||||
| -rw-r--r-- | include/asm-mips/sn/sn0/hubio.h | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/include/asm-mips/mach-excite/excite_fpga.h b/include/asm-mips/mach-excite/excite_fpga.h index 38fcda7..0a1ef69 100644 --- a/include/asm-mips/mach-excite/excite_fpga.h +++ b/include/asm-mips/mach-excite/excite_fpga.h @@ -3,7 +3,7 @@ /** - * Adress alignment of the individual FPGA bytes. + * Address alignment of the individual FPGA bytes. * The address arrangement of the individual bytes of the FPGA is two * byte aligned at the embedded MK2 platform. */ diff --git a/include/asm-mips/mach-wrppmc/mach-gt64120.h b/include/asm-mips/mach-wrppmc/mach-gt64120.h index 00d8bf6..83746b8 100644 --- a/include/asm-mips/mach-wrppmc/mach-gt64120.h +++ b/include/asm-mips/mach-wrppmc/mach-gt64120.h @@ -45,7 +45,7 @@ #define GT_PCI_IO_SIZE 0x02000000UL /* - * PCI interrupts will come in on either the INTA or INTD interrups lines, + * PCI interrupts will come in on either the INTA or INTD interrupt lines, * which are mapped to the #2 and #5 interrupt pins of the MIPS. On our * boards, they all either come in on IntD or they all come in on IntA, they * aren't mixed. There can be numerous PCI interrupts, so we keep a list of the diff --git a/include/asm-mips/sgi/ip22.h b/include/asm-mips/sgi/ip22.h index f4981c4..c0501f9 100644 --- a/include/asm-mips/sgi/ip22.h +++ b/include/asm-mips/sgi/ip22.h @@ -15,7 +15,7 @@ /* * These are the virtual IRQ numbers, we divide all IRQ's into * 'spaces', the 'space' determines where and how to enable/disable - * that particular IRQ on an SGI machine. HPC DMA and MC DMA interrups + * that particular IRQ on an SGI machine. HPC DMA and MC DMA interrupts * are not supported this way. Driver is supposed to allocate HPC/MC * interrupt as shareable and then look to proper status bit (see * HAL2 driver). This will prevent many complications, trust me ;-) diff --git a/include/asm-mips/sn/sn0/hubio.h b/include/asm-mips/sn/sn0/hubio.h index ef91b33..0187895 100644 --- a/include/asm-mips/sn/sn0/hubio.h +++ b/include/asm-mips/sn/sn0/hubio.h @@ -338,7 +338,7 @@ typedef union io_perf_cnt { #define IIO_IFDR 0x400398 /* IOQ FIFO Depth */ #define IIO_IIAP 0x4003a0 /* IIQ Arbitration Parameters */ #define IIO_IMMR IIO_IIAP -#define IIO_ICMR 0x4003a8 /* CRB Managment Register */ +#define IIO_ICMR 0x4003a8 /* CRB Management Register */ #define IIO_ICCR 0x4003b0 /* CRB Control Register */ #define IIO_ICTO 0x4003b8 /* CRB Time Out Register */ #define IIO_ICTP 0x4003c0 /* CRB Time Out Prescalar */ |