[GPIO] add gpio macro & define

2 files changed, 77 insertions, 2 deletions

diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h
index f69b6c3..321689b 100644
--- a/arch/arm/mach-s5pv210/include/mach/irqs.h
+++ b/arch/arm/mach-s5pv210/include/mach/irqs.h
@@ -136,13 +136,13 @@
 
 #define S5P_EINT_BASE1		(S5P_IRQ_VIC0(0))
 #define S5P_EINT_BASE2		(IRQ_VIC_END + 1)
+#define S5P_IRQ_EINT_BASE   S5P_EINT_BASE2
 
 /* GPIO interrupt */
 #define S5P_GPIOINT_BASE	(IRQ_EINT(31) + 1)
 #define S5P_GPIOINT_GROUP_MAXNR	22
 
-/* Set the default NR_IRQS */
-#define NR_IRQS			(IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
+#define S5P_EINT(x)    ((x) + S5P_IRQ_EINT_BASE)
 
 /* Compatibility */
 #define IRQ_LCD_FIFO		IRQ_LCD0
@@ -150,4 +150,71 @@
 #define IRQ_LCD_SYSTEM		IRQ_LCD2
 #define IRQ_MIPI_CSIS0		IRQ_MIPI_CSIS
 
+/* Next the external interrupt groups. These are similar to the IRQ_EINT(x)
+ * that they are sourced from the GPIO pins but with a different scheme for
+ * priority and source indication.
+ *
+ * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO
+ * interrupts, but for historical reasons they are kept apart from these
+ * next interrupts.
+ *
+ * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the
+ * machine specific support files.
+ */
+
+#define IRQ_EINT_GROUP1_NR	(8)	/* A0 */
+#define IRQ_EINT_GROUP2_NR	(4)	/* A1 */
+#define IRQ_EINT_GROUP3_NR	(8)     /* B */
+#define IRQ_EINT_GROUP4_NR	(5)     /* C0 */
+#define IRQ_EINT_GROUP5_NR	(5)     /* C1 */
+#define IRQ_EINT_GROUP6_NR	(4)     /* D0 */
+#define IRQ_EINT_GROUP7_NR	(6)     /* D1 */
+#define IRQ_EINT_GROUP8_NR	(8)     /* E0 */
+#define IRQ_EINT_GROUP9_NR	(5)     /* E1 */
+#define IRQ_EINT_GROUP10_NR	(8)     /* F0 */
+#define IRQ_EINT_GROUP11_NR	(8)     /* F1 */
+#define IRQ_EINT_GROUP12_NR	(8)     /* F2 */
+#define IRQ_EINT_GROUP13_NR	(6)     /* F3 */
+#define IRQ_EINT_GROUP14_NR	(7)     /* G0 */
+#define IRQ_EINT_GROUP15_NR	(7)     /* G1 */
+#define IRQ_EINT_GROUP16_NR	(7)     /* G2 */
+#define IRQ_EINT_GROUP17_NR	(7)     /* G3 */
+#define IRQ_EINT_GROUP18_NR	(8)     /* J0 */
+#define IRQ_EINT_GROUP19_NR	(6)     /* J1 */
+#define IRQ_EINT_GROUP20_NR	(8)     /* J2 */
+#define IRQ_EINT_GROUP21_NR	(8)     /* J3 */
+#define IRQ_EINT_GROUP22_NR	(5)     /* J4 */
+
+#define IRQ_EINT_GROUP_BASE	S5P_EINT(31 + 1)
+#define IRQ_EINT_GROUP1_BASE	(IRQ_EINT_GROUP_BASE + 0x00)
+#define IRQ_EINT_GROUP2_BASE	(IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR)
+#define IRQ_EINT_GROUP3_BASE	(IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR)
+#define IRQ_EINT_GROUP4_BASE	(IRQ_EINT_GROUP3_BASE + IRQ_EINT_GROUP3_NR)
+#define IRQ_EINT_GROUP5_BASE	(IRQ_EINT_GROUP4_BASE + IRQ_EINT_GROUP4_NR)
+#define IRQ_EINT_GROUP6_BASE	(IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR)
+#define IRQ_EINT_GROUP7_BASE	(IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR)
+#define IRQ_EINT_GROUP8_BASE	(IRQ_EINT_GROUP7_BASE + IRQ_EINT_GROUP7_NR)
+#define IRQ_EINT_GROUP9_BASE	(IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR)
+#define IRQ_EINT_GROUP10_BASE	(IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR)
+#define IRQ_EINT_GROUP11_BASE	(IRQ_EINT_GROUP10_BASE + IRQ_EINT_GROUP10_NR)
+#define IRQ_EINT_GROUP12_BASE	(IRQ_EINT_GROUP11_BASE + IRQ_EINT_GROUP11_NR)
+#define IRQ_EINT_GROUP13_BASE	(IRQ_EINT_GROUP12_BASE + IRQ_EINT_GROUP12_NR)
+#define IRQ_EINT_GROUP14_BASE	(IRQ_EINT_GROUP13_BASE + IRQ_EINT_GROUP13_NR)
+#define IRQ_EINT_GROUP15_BASE	(IRQ_EINT_GROUP14_BASE + IRQ_EINT_GROUP14_NR)
+#define IRQ_EINT_GROUP16_BASE	(IRQ_EINT_GROUP15_BASE + IRQ_EINT_GROUP15_NR)
+#define IRQ_EINT_GROUP17_BASE	(IRQ_EINT_GROUP16_BASE + IRQ_EINT_GROUP16_NR)
+#define IRQ_EINT_GROUP18_BASE	(IRQ_EINT_GROUP17_BASE + IRQ_EINT_GROUP17_NR)
+#define IRQ_EINT_GROUP19_BASE	(IRQ_EINT_GROUP18_BASE + IRQ_EINT_GROUP18_NR)
+#define IRQ_EINT_GROUP20_BASE	(IRQ_EINT_GROUP19_BASE + IRQ_EINT_GROUP19_NR)
+#define IRQ_EINT_GROUP21_BASE	(IRQ_EINT_GROUP20_BASE + IRQ_EINT_GROUP20_NR)
+#define IRQ_EINT_GROUP22_BASE	(IRQ_EINT_GROUP21_BASE + IRQ_EINT_GROUP21_NR)
+
+#define IRQ_EINT_GROUP(group, no)	(IRQ_EINT_GROUP##group##_BASE + (no))
+
+/* Set the default NR_IRQS */
+//#define NR_IRQS			(IRQ_EINT(31) + 1)
+#define NR_IRQS		(IRQ_EINT_GROUP22_BASE + IRQ_EINT_GROUP22_NR + 1)
+
+#define HALL_SENSOR_IRQ		IRQ_EINT3
+
 #endif /* ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-gpio.h b/arch/arm/mach-s5pv210/include/mach/regs-gpio.h
index 1669549..7d79ea3 100644
--- a/arch/arm/mach-s5pv210/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s5pv210/include/mach/regs-gpio.h
@@ -248,8 +248,16 @@
 
 #define EINT_REG_NR(x)			(EINT_OFFSET(x) >> 3)
 
+#define eint_offset(irq)		((irq) < IRQ_EINT16_31 ? ((irq)-IRQ_EINT0)\
+						: (irq-S5P_IRQ_EINT_BASE))
+
 #define eint_irq_to_bit(irq)		(1 << (EINT_OFFSET(irq) & 0x7))
 
+#define eint_conf_reg(irq)		((eint_offset(irq)) >> 3)
+#define eint_filt_reg(irq)		((eint_offset(irq)) >> 2)
+#define eint_mask_reg(irq)		((eint_offset(irq)) >> 3)
+#define eint_pend_reg(irq)		((eint_offset(irq)) >> 3)
+
 #define EINT_MODE		S3C_GPIO_SFN(0xf)
 
 #define EINT_GPIO_0(x)		S5PV210_GPH0(x)