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| author | Catalin Marinas <catalin.marinas@arm.com> | 2010-03-24 16:48:53 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-03-25 21:13:50 +0000 |
| commit | 23107c542068b2b94390aa333f6b330af64961e4 (patch) | |
| tree | 8730f15e805ec2c02aaf6eac1780dcdbe22c2c04 /arch/arm/mm | |
| parent | 319f551a0a167b49b5bbb4a9ff4802046a572bc5 (diff) | |
| download | kernel_samsung_crespo-23107c542068b2b94390aa333f6b330af64961e4.zip kernel_samsung_crespo-23107c542068b2b94390aa333f6b330af64961e4.tar.gz kernel_samsung_crespo-23107c542068b2b94390aa333f6b330af64961e4.tar.bz2 | |
ARM: 5995/1: ARM: Add L2x0 outer_sync() support (3/4)
The L2x0 cache controllers need to explicitly drain their write buffer
even for Normal Noncacheable memory accesses.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm')
| -rw-r--r-- | arch/arm/mm/Kconfig | 1 | ||||
| -rw-r--r-- | arch/arm/mm/cache-l2x0.c | 10 |
2 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 88a24de..55a2a00 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -763,6 +763,7 @@ config CACHE_L2X0 REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || ARCH_NOMADIK || ARCH_OMAP4 default y select OUTER_CACHE + select OUTER_CACHE_SYNC help This option enables the L2x0 PrimeCell. diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 0733463..21ad68b 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -93,6 +93,15 @@ static inline void l2x0_flush_line(unsigned long addr) } #endif +static void l2x0_cache_sync(void) +{ + unsigned long flags; + + spin_lock_irqsave(&l2x0_lock, flags); + cache_sync(); + spin_unlock_irqrestore(&l2x0_lock, flags); +} + static inline void l2x0_inv_all(void) { unsigned long flags; @@ -225,6 +234,7 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) outer_cache.inv_range = l2x0_inv_range; outer_cache.clean_range = l2x0_clean_range; outer_cache.flush_range = l2x0_flush_range; + outer_cache.sync = l2x0_cache_sync; printk(KERN_INFO "L2X0 cache controller enabled\n"); } |