diff options
| author | minsu78.kim <minsu78.kim@samsung.com> | 2010-09-01 17:11:40 -0700 |
|---|---|---|
| committer | Arve Hjønnevåg <arve@android.com> | 2011-11-17 17:43:52 -0800 |
| commit | f7b616f3f10258180e3822510ee5ea37aae8fccf (patch) | |
| tree | ad038be5e8c6225ea16104f907a5365b75aa8dda /arch/arm/plat-samsung | |
| parent | 23a2f341353a2b1841efbcc940926d735424b537 (diff) | |
| download | kernel_samsung_crespo-f7b616f3f10258180e3822510ee5ea37aae8fccf.zip kernel_samsung_crespo-f7b616f3f10258180e3822510ee5ea37aae8fccf.tar.gz kernel_samsung_crespo-f7b616f3f10258180e3822510ee5ea37aae8fccf.tar.bz2 | |
S5PC110: PM: add save/restore gpio drivestrength
The gpio drivestrength registers of S5PC110 are cleared at wakeup from sleep
So the drivestrength register must be saved before sleep,
and restore the values after wakeup.
Change-Id: I9578a50d697333d1e03d65bc44739f8a8389a71f
Signed-off-by: minsu78.kim <minsu78.kim@samsung.com>
Diffstat (limited to 'arch/arm/plat-samsung')
| -rwxr-xr-x[-rw-r--r--] | arch/arm/plat-samsung/include/plat/gpio-core.h | 2 | ||||
| -rwxr-xr-x[-rw-r--r--] | arch/arm/plat-samsung/pm-gpio.c | 3 |
2 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h index 8cad4cf..bc0edc3 100644..100755 --- a/arch/arm/plat-samsung/include/plat/gpio-core.h +++ b/arch/arm/plat-samsung/include/plat/gpio-core.h @@ -69,7 +69,7 @@ struct s3c_gpio_chip { int group; spinlock_t lock; #ifdef CONFIG_PM - u32 pm_save[4]; + u32 pm_save[5]; #endif }; diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c index 9652820..566a6c0 100644..100755 --- a/arch/arm/plat-samsung/pm-gpio.c +++ b/arch/arm/plat-samsung/pm-gpio.c @@ -27,6 +27,7 @@ #define OFFS_CON (0x00) #define OFFS_DAT (0x04) #define OFFS_UP (0x08) +#define OFFS_DRV (0x0C) static void s3c_gpio_pm_1bit_save(struct s3c_gpio_chip *chip) { @@ -198,6 +199,7 @@ static void s3c_gpio_pm_4bit_save(struct s3c_gpio_chip *chip) chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON); chip->pm_save[2] = __raw_readl(chip->base + OFFS_DAT); chip->pm_save[3] = __raw_readl(chip->base + OFFS_UP); + chip->pm_save[4] = __raw_readl(chip->base + OFFS_DRV); if (chip->chip.ngpio > 8) chip->pm_save[0] = __raw_readl(chip->base - 4); @@ -284,6 +286,7 @@ static void s3c_gpio_pm_4bit_resume(struct s3c_gpio_chip *chip) __raw_writel(chip->pm_save[2], base + OFFS_DAT); __raw_writel(chip->pm_save[3], base + OFFS_UP); + __raw_writel(chip->pm_save[4], base + OFFS_DRV); if (chip->chip.ngpio > 8) { S3C_PMDBG("%s: CON4 %08x,%08x => %08x,%08x, DAT %08x => %08x\n", |