S5PC110: APM: Add Power Management Support

This patch adds suspend-to-ram support for S5PC110.

Signed-off-by: Sungjun Bae <june.bae@samsung.com>

8 files changed, 29 insertions, 593 deletions

diff --git a/arch/arm/mach-s5pv210/include/mach/pm-core.h b/arch/arm/mach-s5pv210/include/mach/pm-core.h
index a93c1a2..ca3f827 100644
--- a/arch/arm/mach-s5pv210/include/mach/pm-core.h
+++ b/arch/arm/mach-s5pv210/include/mach/pm-core.h
@@ -1,11 +1,14 @@
 /* linux/arch/arm/mach-s5pv210/include/mach/pm-core.h
  *
  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ *		http://www.samsung.com
  *
- * Based on arch/arm/plat-s3c24xx/include/plat/pm-core.h,
- * Copyright 2008-2009 Simtec Electronics Ben Dooks <ben@simtec.co.uk>
- * S5P series driver for power management
+ * Based on arch/arm/mach-s3c2410/include/mach/pm-core.h,
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S5PV210 - PM core support for arch/arm/plat-s5p/pm.c
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -14,38 +17,28 @@
 
 static inline void s3c_pm_debug_init_uart(void)
 {
+	/* nothing here yet */
 }
 
 static inline void s3c_pm_arch_prepare_irqs(void)
 {
 	__raw_writel(s3c_irqwake_intmask, S5P_WAKEUP_MASK);
 	__raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK);
-
-	/* ack any outstanding external interrupts before we go to sleep */
-
 }
 
 static inline void s3c_pm_arch_stop_clocks(void)
 {
+	/* nothing here yet */
 }
 
-static void s3c_pm_show_resume_irqs(int start, unsigned long which,
-				    unsigned long mask);
-
 static inline void s3c_pm_arch_show_resume_irqs(void)
 {
+	/* nothing here yet */
 }
 
-/* make these defines, we currently do not have any need to change
- * the IRQ wake controls depending on the CPU we are running on */
-
-/* 2009.04.27 by icarus : don't use this definition, use extern var */
-#if 0
-#define s3c_irqwake_eintallow	(0xFFFFFFFF)
-#define s3c_irqwake_intallow	(0)
-#endif
-
 static inline void s3c_pm_arch_update_uart(void __iomem *regs,
 					   struct pm_uart_save *save)
 {
+	/* nothing here yet */
 }
+
diff --git a/arch/arm/mach-s5pv210/mach-herring.c b/arch/arm/mach-s5pv210/mach-herring.c
index 3dfcfb9..0fb3c24 100644
--- a/arch/arm/mach-s5pv210/mach-herring.c
+++ b/arch/arm/mach-s5pv210/mach-herring.c
@@ -3036,7 +3036,6 @@ static void __init herring_machine_init(void)
 	//s3c_device_onenand.dev.platform_data = &s5p_onenand_data;
 #endif
 
-
 	qt_touch_init();
 
 #ifdef CONFIG_DM9000
@@ -3094,12 +3093,10 @@ static void __init herring_machine_init(void)
 	s3c_adc_set_platdata(&s3c_adc_platform);
 #endif
 
-#if 0 /* will be initialized at pm.c */
 #if defined(CONFIG_PM)
 	s3c_pm_init();
 //	s5pc11x_pm_init();
 #endif
-#endif
 
 #ifdef CONFIG_VIDEO_FIMC
 	/* fimc */
diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c
index 24febae..8afcef9 100644
--- a/arch/arm/mach-s5pv210/pm.c
+++ b/arch/arm/mach-s5pv210/pm.c
@@ -130,6 +130,11 @@ static void s5pv210_pm_prepare(void)
 	tmp |= S5P_OTHER_SYSC_INTOFF;
 	__raw_writel(tmp, S5P_OTHERS);
 
+	__raw_writel(0xffffffff, (VA_VIC0 + VIC_INT_ENABLE_CLEAR));
+	__raw_writel(0xffffffff, (VA_VIC1 + VIC_INT_ENABLE_CLEAR));
+	__raw_writel(0xffffffff, (VA_VIC2 + VIC_INT_ENABLE_CLEAR));
+	__raw_writel(0xffffffff, (VA_VIC3 + VIC_INT_ENABLE_CLEAR));
+
 	s3c_pm_do_save(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save));
 }
 
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index 8728b60..a45124a 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -42,9 +42,10 @@ obj-$(CONFIG_S5P_SETUP_MIPIPHY)	+= setup-mipiphy.o
 
 # PM support
 
+# PM support
+
 obj-$(CONFIG_PM)		+= pm.o
 obj-$(CONFIG_PM)		+= irq-pm.o
-obj-$(CONFIG_PM)		+= sleep.o
 
 ifdef CONFIG_S5P_HIGH_RES_TIMERS
 ifdef CONFIG_HRT_RTC
diff --git a/arch/arm/plat-s5p/include/plat/pm.h b/arch/arm/plat-s5p/include/plat/pm.h
index 9c62446..b44c82e 100644
--- a/arch/arm/plat-s5p/include/plat/pm.h
+++ b/arch/arm/plat-s5p/include/plat/pm.h
@@ -17,12 +17,11 @@
 #include <mach/cpuidle.h>
 #endif /* CONFIG_S5P_LPAUDIO */
 
-#ifdef CONFIG_PM
+#if defined(CONFIG_PM)
 
 extern __init int s3c_pm_init(void);
 
 #else
-
 static inline int s3c_pm_init(void)
 {
 	return 0;
diff --git a/arch/arm/plat-s5p/pm.c b/arch/arm/plat-s5p/pm.c
index 242c16b..d15dc47 100644
--- a/arch/arm/plat-s5p/pm.c
+++ b/arch/arm/plat-s5p/pm.c
@@ -1,252 +1,24 @@
 /* linux/arch/arm/plat-s5p/pm.c
  *
  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
+ *		http://www.samsung.com
  *
  * S5P Power Manager (Suspend-To-RAM) support
  *
- * Based on arch/arm/mach-pxa/pm.c
+ * Based on arch/arm/plat-s3c24xx/pm.c
+ * Copyright (c) 2004,2006 Simtec Electronics
+ *	Ben Dooks <ben@simtec.co.uk>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
 */
 
-#include <linux/init.h>
 #include <linux/suspend.h>
-#include <linux/errno.h>
-#include <linux/time.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/crc32.h>
-#include <linux/ioport.h>
-#include <linux/delay.h>
-#include <linux/serial_core.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-
-#include <asm/cacheflush.h>
-#include <mach/hardware.h>
-
-#include <plat/map-base.h>
-#include <plat/regs-serial.h>
-#include <plat/regs-timer.h>
-#include <mach/regs-clock.h>
-#include <plat/gpio-cfg.h>
-#include <mach/regs-mem.h>
-#include <mach/regs-irq.h>
-#include <mach/regs-gpio.h>
-#include <linux/gpio.h>
-#include <asm/mach/time.h>
-
 #include <plat/pm.h>
-#include <mach/irqs.h>
 
 #define PFX "s5p pm: "
 
-static struct sleep_save core_save[] = {
-/* PLL Control */
-	SAVE_ITEM(S5P_APLL_CON),
-	SAVE_ITEM(S5P_MPLL_CON),
-	SAVE_ITEM(S5P_EPLL_CON),
-	SAVE_ITEM(S5P_VPLL_CON),
-/* Clock source */
-	SAVE_ITEM(S5P_CLK_SRC0),
-	SAVE_ITEM(S5P_CLK_SRC1),
-	SAVE_ITEM(S5P_CLK_SRC2),
-	SAVE_ITEM(S5P_CLK_SRC3),
-	SAVE_ITEM(S5P_CLK_SRC4),
-	SAVE_ITEM(S5P_CLK_SRC5),
-	SAVE_ITEM(S5P_CLK_SRC6),
-/* Clock source Mask */
-	SAVE_ITEM(S5P_CLK_SRC_MASK0),
-	SAVE_ITEM(S5P_CLK_SRC_MASK1),
-/* Clock Divider */
-	SAVE_ITEM(S5P_CLK_DIV0),
-	SAVE_ITEM(S5P_CLK_DIV1),
-	SAVE_ITEM(S5P_CLK_DIV2),
-	SAVE_ITEM(S5P_CLK_DIV3),
-	SAVE_ITEM(S5P_CLK_DIV4),
-	SAVE_ITEM(S5P_CLK_DIV5),
-	SAVE_ITEM(S5P_CLK_DIV6),
-	SAVE_ITEM(S5P_CLK_DIV7),
-/* Clock Main Main Gate */
-	SAVE_ITEM(S5P_CLKGATE_MAIN0),
-	SAVE_ITEM(S5P_CLKGATE_MAIN1),
-	SAVE_ITEM(S5P_CLKGATE_MAIN2),
-/* Clock source Peri Gate */
-	SAVE_ITEM(S5P_CLKGATE_PERI0),
-	SAVE_ITEM(S5P_CLKGATE_PERI1),
-/* Clock source SCLK Gate */
-	SAVE_ITEM(S5P_CLKGATE_SCLK0),
-	SAVE_ITEM(S5P_CLKGATE_SCLK1),
-/* Clock IP Clock gate */
-	SAVE_ITEM(S5P_CLKGATE_IP0),
-	SAVE_ITEM(S5P_CLKGATE_IP1),
-	SAVE_ITEM(S5P_CLKGATE_IP2),
-	SAVE_ITEM(S5P_CLKGATE_IP3),
-	SAVE_ITEM(S5P_CLKGATE_IP4),
-/* Clock Blcok and Bus gate */
-	SAVE_ITEM(S5P_CLKGATE_BLOCK),
-	SAVE_ITEM(S5P_CLKGATE_BUS0),
-/* Clock ETC */
-	SAVE_ITEM(S5P_CLK_OUT),
-	SAVE_ITEM(S5P_MDNIE_SEL),
-/* PWM Register */
-	SAVE_ITEM(S3C2410_TCFG0),
-	SAVE_ITEM(S3C2410_TCFG1),
-	SAVE_ITEM(S3C64XX_TINT_CSTAT),
-	SAVE_ITEM(S3C2410_TCON),
-	SAVE_ITEM(S3C2410_TCNTB(0)),
-	SAVE_ITEM(S3C2410_TCMPB(0)),
-	SAVE_ITEM(S3C2410_TCNTO(0)),
-};
-
-static struct sleep_save sromc_save[] = {
-	SAVE_ITEM(S5P_SROM_BW),
-	SAVE_ITEM(S5P_SROM_BC0),
-	SAVE_ITEM(S5P_SROM_BC1),
-	SAVE_ITEM(S5P_SROM_BC2),
-	SAVE_ITEM(S5P_SROM_BC3),
-	SAVE_ITEM(S5P_SROM_BC4),
-	SAVE_ITEM(S5P_SROM_BC5),
-};
- 
-static struct sleep_save gpio_save_ext[] = {
-
-	SAVE_ITEM(S5P_EINT_CON(0)),
-	SAVE_ITEM(S5P_EINT_CON(1)),
-	SAVE_ITEM(S5P_EINT_CON(2)),
-	SAVE_ITEM(S5P_EINT_CON(3)),
-
-	SAVE_ITEM(S5P_EINT_MASK(0)),
-	SAVE_ITEM(S5P_EINT_MASK(1)),
-	SAVE_ITEM(S5P_EINT_MASK(2)),
-	SAVE_ITEM(S5P_EINT_MASK(3)),
-
-	SAVE_ITEM(S5P_EINT_FLTCON(0,0)),
-	SAVE_ITEM(S5P_EINT_FLTCON(0,1)),
-	SAVE_ITEM(S5P_EINT_FLTCON(1,0)),
-	SAVE_ITEM(S5P_EINT_FLTCON(1,1)),
-	SAVE_ITEM(S5P_EINT_FLTCON(2,0)),
-	SAVE_ITEM(S5P_EINT_FLTCON(2,1)),
-	SAVE_ITEM(S5P_EINT_FLTCON(3,0)),
-	SAVE_ITEM(S5P_EINT_FLTCON(3,1)),
-};
-
-/*gpio group interrupt*/
-static struct sleep_save gpio_save_gpio_int[] = {
-
-	SAVE_ITEM(S5PV210_GPA0_INT_CON),
-	SAVE_ITEM(S5PV210_GPA1_INT_CON),
-	SAVE_ITEM(S5PV210_GPB_INT_CON),
-	SAVE_ITEM(S5PV210_GPC0_INT_CON),
-	SAVE_ITEM(S5PV210_GPC1_INT_CON),
-	SAVE_ITEM(S5PV210_GPD0_INT_CON),
-	SAVE_ITEM(S5PV210_GPD1_INT_CON),
-	SAVE_ITEM(S5PV210_GPE0_INT_CON),
-	SAVE_ITEM(S5PV210_GPE1_INT_CON),
-	SAVE_ITEM(S5PV210_GPF0_INT_CON),
-	SAVE_ITEM(S5PV210_GPF1_INT_CON),
-	SAVE_ITEM(S5PV210_GPF2_INT_CON),
-	SAVE_ITEM(S5PV210_GPF3_INT_CON),
-	SAVE_ITEM(S5PV210_GPG0_INT_CON),
-	SAVE_ITEM(S5PV210_GPG1_INT_CON),
-	SAVE_ITEM(S5PV210_GPG2_INT_CON),
-	SAVE_ITEM(S5PV210_GPG3_INT_CON),
-	SAVE_ITEM(S5PV210_GPJ0_INT_CON),
-	SAVE_ITEM(S5PV210_GPJ1_INT_CON),
-	SAVE_ITEM(S5PV210_GPJ2_INT_CON),
-	SAVE_ITEM(S5PV210_GPJ3_INT_CON),
-	SAVE_ITEM(S5PV210_GPJ4_INT_CON),
-
-	SAVE_ITEM(S5PV210_GPA0_INT_MASK),
-	SAVE_ITEM(S5PV210_GPA1_INT_MASK),
-	SAVE_ITEM(S5PV210_GPB_INT_MASK),
-	SAVE_ITEM(S5PV210_GPC0_INT_MASK),
-	SAVE_ITEM(S5PV210_GPC1_INT_MASK),
-	SAVE_ITEM(S5PV210_GPD0_INT_MASK),
-	SAVE_ITEM(S5PV210_GPD1_INT_MASK),
-	SAVE_ITEM(S5PV210_GPE0_INT_MASK),
-	SAVE_ITEM(S5PV210_GPE1_INT_MASK),
-	SAVE_ITEM(S5PV210_GPF0_INT_MASK),
-	SAVE_ITEM(S5PV210_GPF1_INT_MASK),
-	SAVE_ITEM(S5PV210_GPF2_INT_MASK),
-	SAVE_ITEM(S5PV210_GPF3_INT_MASK),
-	SAVE_ITEM(S5PV210_GPG0_INT_MASK),
-	SAVE_ITEM(S5PV210_GPG1_INT_MASK),
-	SAVE_ITEM(S5PV210_GPG2_INT_MASK),
-	SAVE_ITEM(S5PV210_GPG3_INT_MASK),
-	SAVE_ITEM(S5PV210_GPJ0_INT_MASK),
-	SAVE_ITEM(S5PV210_GPJ1_INT_MASK),
-	SAVE_ITEM(S5PV210_GPJ2_INT_MASK),
-	SAVE_ITEM(S5PV210_GPJ3_INT_MASK),
-	SAVE_ITEM(S5PV210_GPJ4_INT_MASK),
-
-	SAVE_ITEM(S5PV210_GPA0_INT_FLTCON0),
-	SAVE_ITEM(S5PV210_GPA0_INT_FLTCON1),
-	SAVE_ITEM(S5PV210_GPA1_INT_FLTCON0),
-	SAVE_ITEM(S5PV210_GPA1_INT_FLTCON1),
-	SAVE_ITEM(S5PV210_GPB_INT_FLTCON0),
-	SAVE_ITEM(S5PV210_GPB_INT_FLTCON1),
-	SAVE_ITEM(S5PV210_GPC0_INT_FLTCON0),
-	SAVE_ITEM(S5PV210_GPC0_INT_FLTCON1),
-	SAVE_ITEM(S5PV210_GPC1_INT_FLTCON0),
-	SAVE_ITEM(S5PV210_GPC1_INT_FLTCON1),
-	SAVE_ITEM(S5PV210_GPD0_INT_FLTCON0),
-	SAVE_ITEM(S5PV210_GPD0_INT_FLTCON1),
-	SAVE_ITEM(S5PV210_GPD1_INT_FLTCON0),
-	SAVE_ITEM(S5PV210_GPD1_INT_FLTCON1),
-	SAVE_ITEM(S5PV210_GPE0_INT_FLTCON0),
-	SAVE_ITEM(S5PV210_GPE0_INT_FLTCON1),
-	SAVE_ITEM(S5PV210_GPE1_INT_FLTCON0),
-	SAVE_ITEM(S5PV210_GPE1_INT_FLTCON1),
-	SAVE_ITEM(S5PV210_GPF0_INT_FLTCON0),
-	SAVE_ITEM(S5PV210_GPF0_INT_FLTCON1),
-	SAVE_ITEM(S5PV210_GPF1_INT_FLTCON0),
-	SAVE_ITEM(S5PV210_GPF1_INT_FLTCON1),
-	SAVE_ITEM(S5PV210_GPF2_INT_FLTCON0),
-	SAVE_ITEM(S5PV210_GPF2_INT_FLTCON1),
-	SAVE_ITEM(S5PV210_GPF3_INT_FLTCON0),
-	SAVE_ITEM(S5PV210_GPF3_INT_FLTCON1),
-	SAVE_ITEM(S5PV210_GPG0_INT_FLTCON0),
-	SAVE_ITEM(S5PV210_GPG0_INT_FLTCON1),
-	SAVE_ITEM(S5PV210_GPG1_INT_FLTCON0),
-	SAVE_ITEM(S5PV210_GPG1_INT_FLTCON1),
-	SAVE_ITEM(S5PV210_GPG2_INT_FLTCON0),
-	SAVE_ITEM(S5PV210_GPG2_INT_FLTCON1),
-	SAVE_ITEM(S5PV210_GPG3_INT_FLTCON0),
-	SAVE_ITEM(S5PV210_GPG3_INT_FLTCON1),
-	SAVE_ITEM(S5PV210_GPJ0_INT_FLTCON0),
-	SAVE_ITEM(S5PV210_GPJ0_INT_FLTCON1),
-	SAVE_ITEM(S5PV210_GPJ1_INT_FLTCON0),
-	SAVE_ITEM(S5PV210_GPJ1_INT_FLTCON1),
-	SAVE_ITEM(S5PV210_GPJ2_INT_FLTCON0),
-	SAVE_ITEM(S5PV210_GPJ2_INT_FLTCON1),
-	SAVE_ITEM(S5PV210_GPJ3_INT_FLTCON0),
-	SAVE_ITEM(S5PV210_GPJ3_INT_FLTCON1),
-	SAVE_ITEM(S5PV210_GPJ4_INT_FLTCON0),
-	SAVE_ITEM(S5PV210_GPJ4_INT_FLTCON1),
-
-};
-
-/* this lot should be really saved by the IRQ code */
-/* VICXADDRESSXX initilaization to be needed */
-static struct sleep_save irq_save[] = {
-	SAVE_ITEM(S5P_VIC0REG(VIC_INT_SELECT)),
-	SAVE_ITEM(S5P_VIC1REG(VIC_INT_SELECT)),
-	SAVE_ITEM(S5P_VIC2REG(VIC_INT_SELECT)),
-	SAVE_ITEM(S5P_VIC3REG(VIC_INT_SELECT)),
-	SAVE_ITEM(S5P_VIC0REG(VIC_INT_ENABLE)),
-	SAVE_ITEM(S5P_VIC1REG(VIC_INT_ENABLE)),
-	SAVE_ITEM(S5P_VIC2REG(VIC_INT_ENABLE)),
-	SAVE_ITEM(S5P_VIC3REG(VIC_INT_ENABLE)),
-	SAVE_ITEM(S5P_VIC0REG(VIC_INT_SOFT)),
-	SAVE_ITEM(S5P_VIC1REG(VIC_INT_SOFT)),
-	SAVE_ITEM(S5P_VIC2REG(VIC_INT_SOFT)),
-	SAVE_ITEM(S5P_VIC3REG(VIC_INT_SOFT)),
-};
-
 /* s3c_pm_configure_extint
  *
  * configure all external interrupt pins
@@ -254,30 +26,16 @@ static struct sleep_save irq_save[] = {
 
 void s3c_pm_configure_extint(void)
 {
-
-	/* for each of the external interrupts (EINT0..EINT15) we
-	 * need to check wether it is an external interrupt source,
-	 * and then configure it as an input if it is not
-	*/
-	__raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK);
+	/* nothing here yet */
 }
 
-
 void s3c_pm_restore_core(void)
 {
-	s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
-	s3c_pm_do_restore(sromc_save, ARRAY_SIZE(sromc_save));
-	s3c_pm_do_restore(gpio_save_ext, ARRAY_SIZE(gpio_save_ext));
-	s3c_pm_do_restore(gpio_save_gpio_int, ARRAY_SIZE(gpio_save_gpio_int));
-	s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
+	/* nothing here yet */
 }
 
 void s3c_pm_save_core(void)
 {
-	s3c_pm_do_save(sromc_save, ARRAY_SIZE(sromc_save));
-	s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
-	s3c_pm_do_save(gpio_save_ext, ARRAY_SIZE(gpio_save_ext));
-	s3c_pm_do_save(gpio_save_gpio_int, ARRAY_SIZE(gpio_save_gpio_int));
-	s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
+	/* nothing here yet */
 }
 
diff --git a/arch/arm/plat-s5p/sleep.S b/arch/arm/plat-s5p/sleep.S
deleted file mode 100644
index db1b819..0000000
--- a/arch/arm/plat-s5p/sleep.S
+++ /dev/null
@@ -1,319 +0,0 @@
-/* linux/arch/arm/plat-s5p/sleep.S
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5PV210 power Manager (Suspend-To-RAM) support
- * Based on S3C2410 sleep code by:
- * 	Ben Dooks, (c) 2004 Simtec Electronics
- *
- * Based on PXA/SA1100 sleep code by:
- *	Nicolas Pitre, (c) 2002 Monta Vista Software Inc
- *	Cliff Brake, (c) 2001
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-#include <mach/hardware.h>
-#include <mach/map.h>
-#include <asm/asm-offsets.h>
-#include <asm/memory.h>
-#include <asm/system.h>
-
-#include <mach/regs-gpio.h>
-#include <mach/regs-clock.h>
-#include <mach/regs-mem.h>
-#include <plat/regs-serial.h>
-
-#define NO_L2_CLEAN
-
-/* CONFIG_DEBUG_RESUME is dangerous if your bootloader does not
- * reset the UART configuration, only enable if you really need this!
-*/
-	.text
-
-	/* s3c_cpu_save
-	 *
-	 * entry:
-	 *	r0 = save address (virtual addr of s3c_sleep_save_phys)
-	*/
-
-ENTRY(s3c_cpu_save)
-
-	stmfd	sp!, { r3 - r12, lr }
-
-	mrc	p15, 0, r4, c13, c0, 0	@ FCSE/PID
-	mrc	p15, 0, r5, c3, c0, 0	@ Domain ID
-	mrc	p15, 0, r6, c2, c0, 0	@ Translation Table BASE0
-	mrc	p15, 0, r7, c2, c0, 1	@ Translation Table BASE1
-	mrc	p15, 0, r8, c2, c0, 2	@ Translation Table Control
-	mrc	p15, 0, r9, c1, c0, 0	@ Control register
-	mrc	p15, 0, r10, c1, c0, 1	@ Auxiliary control register
-	mrc	p15, 0, r11, c1, c0, 2	@ Co-processor access controls
-	mrc	p15, 0, r12, c10, c2, 0	@ Read PRRR
-	mrc	p15, 0, r3, c10, c2, 1	@ READ NMRR
-
-	ldr	r2, =S5P_INFORM1
-	ldr	r1, [r2]
-	cmp	r1, #0x0
-	bne	idle2_save
-
-	stmia	r0, { r3 - r13 }
-
-	@@ write our state back to RAM
-	bl	s3c_pm_cb_flushcache
-
-	@@ jump to final code to send system to sleep
-	ldr	r0, =pm_cpu_sleep
-	@@ldr	pc, [ r0 ]
-	ldr	r0, [ r0 ]
-	mov	pc, r0
-
-idle2_save:
-	/* Save CP15 registers */
-	stmia	r0!, { r3 - r12}
-
-	/* Save SVC status register */
-	mrs	r2, spsr
-	str	r2, [r0], #4
-
-	/* Save FIQ mode register */
-	mov	r1, #PSR_I_BIT | PSR_F_BIT | FIQ_MODE
-	msr	cpsr_c, r1
-	mrs	r2, spsr
-	stmia	r0!, {r2, r8 - r12, sp, lr }
-
-	/* Save ABT mode register */
-	mov	r1, #PSR_I_BIT | PSR_F_BIT | ABT_MODE
-	msr	cpsr_c, r1
-	mrs	r2, spsr
-	stmia	r0!, {r2, sp, lr }
-
-	/* Save IRQ mode register */
-	mov	r1, #PSR_I_BIT | PSR_F_BIT | IRQ_MODE
-	msr	cpsr_c, r1
-	mrs	r2, spsr
-	stmia	r0!, {r2, sp, lr }
-
-	/* Save UND mode register */
-	mov	r1, #PSR_I_BIT | PSR_F_BIT | UND_MODE
-	msr	cpsr_c, r1
-	mrs	r2, spsr
-	stmia	r0!, {r2, sp, lr }
-#if 0
-	/* Save SYS mode register */
-	mov	r1, #PSR_I_BIT | PSR_F_BIT | SYSTEM_MODE
-	msr	cpsr_c, r1
-	stmia	r0!, {sp, lr }
-#endif
-	/* Return to SVC mode */
-	mov	r1, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
-	msr	cpsr_c, r1
-
-	/* Save SVC mode stack pointer register (R13) */
-	str	r13, [r0]
-
-	mov 	r0, #0
-	ldmfd	sp, { r3 - r12, pc }
-
-	@@ return to the caller, after having the MMU
-	@@ turned on, this restores the last bits from the
-	@@ stack
-resume_with_mmu:
-#if defined(NO_L2_CLEAN)
-	ldr	r0, =S5P_INFORM1
-	ldr	r1, [r0]
-	cmp	r1, #0x0
-	beq	skip_l2_enable
-
-	mrc     p15, 0, r0, c1, c0, 1	@enable L2 cache
-	orr     r0, r0, #(1<<1)
-	mcr     p15, 0, r0, c1, c0, 1
-#endif
-skip_l2_enable:
-	mov	r0, #1
-
-	/* delete added mmu table list */
-	ldr	r9 , =(PAGE_OFFSET - PHYS_OFFSET)
-	add	r4, r4, r9
-	str	r12, [r4]
-
-	ldmfd	sp!, { r3 - r12, pc }
-
-	.ltorg
-
-	@@ the next bits sit in the .data segment, even though they
-	@@ happen to be code... the s5pv210_sleep_save_phys needs to be
-	@@ accessed by the resume code before it can restore the MMU.
-	@@ This means that the variable has to be close enough for the
-	@@ code to read it... since the .text segment needs to be RO,
-	@@ the data segment can be the only place to put this code.
-
-	.data
-
-	.global	s3c_sleep_save_phys
-s3c_sleep_save_phys:
-	.word	0
-
-
-	/* sleep magic, to allow the bootloader to check for an valid
-	 * image to resume to. Must be the first word before the
-	 * s5pv210_cpu_resume entry.
-	*/
-
-	.word	0x2bedf00d
-
-	/* s3c_cpu_resume
-	 *
-	 * resume code entry for bootloader to call
-	 *
-	 * we must put this code here in the data segment as we have no
-	 * other way of restoring the stack pointer after sleep, and we
-	 * must not write to the code segment (code is read-only)
-	*/
-
-ENTRY(s3c_cpu_resume)
-	mov	r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
-	msr	cpsr_c, r0
-
-	@@ load UART to allow us to print the two characters for
-	@@ resume debug
-
-	mov	r1, #0
-	mcr	p15, 0, r1, c8, c7, 0		@@ invalidate TLBs
-	mcr	p15, 0, r1, c7, c5, 0		@@ invalidate I Cache
-
-	ldr	r1, =0xe010f008 	@ Read INFORM2 register
-	ldr	r0, [r1]		@ Load phy_regs_save value
-	ldr	r1, =0xe010f004		@ Read INFORM1 register
-	ldr	r1, [r1]
-	cmp 	r1, #0x0
-	bne	idle2_restore_1
-
-	ldmia	r0, { r3 - r13 }
-	b	common_restore_1
-
-idle2_restore_1:
-	/* Restore CP15 registers */
-	ldmia	r0!, { r3 - r12 }
-
-common_restore_1:
-	mcr	p15, 0, r4, c13, c0, 0	@ FCSE/PID
-	mcr	p15, 0, r5, c3, c0, 0	@ Domain ID
-
-	mcr	p15, 0, r8, c2, c0, 2	@ Translation Table Control
-	mcr	p15, 0, r7, c2, c0, 1	@ Translation Table BASE1
-	mcr	p15, 0, r6, c2, c0, 0	@ Translation Table BASE0
-
-#if defined(NO_L2_CLEAN)
-	cmp	r1, #0x0		@ if idle2 wakeup
-	bicne	r10, r10, #(1<<1)	@ disable L2cache
-	mcr	p15, 0, r10, c1, c0, 1	@ Auxiliary control register
-#endif
-	mov	r1, #0
-	mcr	p15, 0, r1, c8, c7, 0	@ Invalidate I & D TLB
-
-	mov	r1, #0			@ restore copro access controls
-	mcr	p15, 0, r11, c1, c0, 2	@ Co-processor access controls
-	mcr 	p15, 0, r1, c7, c5, 4
-
-	mcr	p15, 0, r12, c10, c2, 0	@ write PRRR
-	mcr	p15, 0, r3, c10, c2, 1	@ write NMRR
-
-	ldr	r1, =0xe010f004		@ Read INFORM1 register
-	ldr	r1, [r1]
-	cmp 	r1, #0x0
-	beq	common_restore_2
-
-	/* Restore SVC status register */
-	ldr	r2, [r0], #4
-	msr	spsr, r2
-
-	/* Restore FIQ mode register */
-	mov	r1, #PSR_I_BIT | PSR_F_BIT | FIQ_MODE
-	msr	cpsr_c, r1
-	ldr	r2, [r0], #4
-	msr	spsr, r2
-	ldmia	r0!, { r8 - r12, sp, lr }
-
-	/* Restore ABT mode register */
-	mov	r1, #PSR_I_BIT | PSR_F_BIT | ABT_MODE
-	msr	cpsr_c, r1
-	ldr	r2, [r0], #4
-	msr	spsr, r2
-	ldmia	r0!, { sp, lr }
-
-	/* Restore IRQ mode register */
-	mov	r1, #PSR_I_BIT | PSR_F_BIT | IRQ_MODE
-	msr	cpsr_c, r1
-	ldr	r2, [r0], #4
-	msr	spsr, r2
-	ldmia	r0!, { sp, lr }
-
-	/* Restore UND mode register */
-	mov	r1, #PSR_I_BIT | PSR_F_BIT | UND_MODE
-	msr	cpsr_c, r1
-	ldr	r2, [r0], #4
-	msr	spsr, r2
-	ldmia	r0!, { sp, lr }
-#if 0
-	/* Restore SYS mode register */
-	mov	r1, #PSR_I_BIT | PSR_F_BIT | SYSTEM_MODE
-	msr	cpsr_c, r1
-	ldmia	r0!, {sp, lr }
-#endif
-	/* Return to SVC mode */
-	mov	r1, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
-	msr	cpsr_c, r1
-
-	/* Restore SVC mode stack pointer register (R13) */
-	ldr	r13, [r0]
-
-common_restore_2:
-	/* calculate first section address into r8 */
-	mov	r4, r6
-	ldr	r5, =0x3fff
-	bic	r4, r4, r5
-	ldr	r11, =0xe010f000
-	ldr	r10, [r11, #0]
-	mov	r10, r10 ,LSR #18
-	bic	r10, r10, #0x3
-	orr	r4, r4, r10
-
-	/* calculate mmu list value into r9 */
-	mov 	r10, r10, LSL #18
-	ldr	r5, =0x40e
-	orr	r10, r10, r5
-
-	/* back up originally data */
-	ldr	r12, [r4]
-
-	/* Added list about mmu */
-	str	r10, [r4]
-
-	ldr	r2, =resume_with_mmu
-	mcr	p15, 0, r9, c1, c0, 0		@ turn on MMU, etc
-
-        nop
-        nop
-        nop
-        nop
-        nop					@ second-to-last before mmu
-
-	mov	pc, r2				@ go back to virtual address
-
-	.ltorg
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
index 5c0a440..60df747 100644
--- a/arch/arm/plat-samsung/pm.c
+++ b/arch/arm/plat-samsung/pm.c
@@ -258,6 +258,8 @@ static int s3c_pm_enter(suspend_state_t state)
 	 * require a full power-cycle)
 	*/
 
+	s3c_irqwake_intmask = 0xFFDD; // key
+
 	if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
 	    !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
 		printk(KERN_ERR "%s: No wake-up sources!\n", __func__);