diff options
| author | Steven King <sfking@fdwdc.com> | 2010-01-22 12:43:03 -0800 |
|---|---|---|
| committer | Greg Ungerer <gerg@uclinux.org> | 2010-05-17 11:04:19 +1000 |
| commit | 91d60417212fa6b100107384c5e4f5663ab69c8f (patch) | |
| tree | 2e751a2df6a8e873b46d800d430d9cf617b9d399 /arch/m68k/include/asm/m527xsim.h | |
| parent | e40152ee1e1c7a63f4777791863215e3faa37a86 (diff) | |
| download | kernel_samsung_crespo-91d60417212fa6b100107384c5e4f5663ab69c8f.zip kernel_samsung_crespo-91d60417212fa6b100107384c5e4f5663ab69c8f.tar.gz kernel_samsung_crespo-91d60417212fa6b100107384c5e4f5663ab69c8f.tar.bz2 | |
m68knommu: Coldfire QSPI platform support
Since Grant has added the coldfire-qspi driver to next-spi, here is the
platform support for the parts that have qspi hardware. This sets up
gpio to do the spi chip select using the default chip select pins; it should
be trivial for boards that require different or additional spi chip selects to
use other gpios as needed.
Signed-off-by: Steven King <sfking@fdwdc.com>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k/include/asm/m527xsim.h')
| -rw-r--r-- | arch/m68k/include/asm/m527xsim.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h index 453356d..1feb46f 100644 --- a/arch/m68k/include/asm/m527xsim.h +++ b/arch/m68k/include/asm/m527xsim.h @@ -31,6 +31,7 @@ #define MCFINT_UART0 13 /* Interrupt number for UART0 */ #define MCFINT_UART1 14 /* Interrupt number for UART1 */ #define MCFINT_UART2 15 /* Interrupt number for UART2 */ +#define MCFINT_QSPI 18 /* Interrupt number for QSPI */ #define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ /* @@ -120,6 +121,9 @@ #define MCFGPIO_PIN_MAX 100 #define MCFGPIO_IRQ_MAX 8 #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE + +#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A) +#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C) #endif #ifdef CONFIG_M5275 @@ -212,6 +216,8 @@ #define MCFGPIO_PIN_MAX 148 #define MCFGPIO_IRQ_MAX 8 #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE + +#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10007E) #endif /* @@ -223,6 +229,7 @@ #define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005) + /* * GPIO pins setups to enable the UARTs. */ |