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| author | Matt Fleming <matt@console-pimps.org> | 2010-03-21 19:51:43 +0000 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2010-03-23 13:36:15 +0900 |
| commit | a9eb4f6d1a168c830a206306dfbb1f95a7fed6b3 (patch) | |
| tree | 6be98ed668898b2659e172e6344eff4178865f84 /arch/sh | |
| parent | 685abecfc2a6036b713229617570980c566c7500 (diff) | |
| download | kernel_samsung_crespo-a9eb4f6d1a168c830a206306dfbb1f95a7fed6b3.zip kernel_samsung_crespo-a9eb4f6d1a168c830a206306dfbb1f95a7fed6b3.tar.gz kernel_samsung_crespo-a9eb4f6d1a168c830a206306dfbb1f95a7fed6b3.tar.bz2 | |
sh: Flush ITLB too in PTEAEX's flush_tlb_page()
flush_tlb_page() can be used to flush TLB entries that map executable
pages. Therefore, we need to ensure that the ITLB is also flushed in
local_flush_tlb_page().
Signed-off-by: Matt Fleming <matt@console-pimps.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh')
| -rw-r--r-- | arch/sh/include/cpu-sh4/cpu/mmu_context.h | 2 | ||||
| -rw-r--r-- | arch/sh/mm/tlb-pteaex.c | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/arch/sh/include/cpu-sh4/cpu/mmu_context.h b/arch/sh/include/cpu-sh4/cpu/mmu_context.h index 03ea75c..310ec92 100644 --- a/arch/sh/include/cpu-sh4/cpu/mmu_context.h +++ b/arch/sh/include/cpu-sh4/cpu/mmu_context.h @@ -19,6 +19,8 @@ #define MMUCR 0xFF000010 /* MMU Control Register */ +#define MMU_ITLB_ADDRESS_ARRAY 0xF2000000 +#define MMU_ITLB_ADDRESS_ARRAY2 0xF2800000 #define MMU_UTLB_ADDRESS_ARRAY 0xF6000000 #define MMU_UTLB_ADDRESS_ARRAY2 0xF6800000 #define MMU_PAGE_ASSOC_BIT 0x80 diff --git a/arch/sh/mm/tlb-pteaex.c b/arch/sh/mm/tlb-pteaex.c index 32dc674..bdd0982 100644 --- a/arch/sh/mm/tlb-pteaex.c +++ b/arch/sh/mm/tlb-pteaex.c @@ -73,5 +73,7 @@ void local_flush_tlb_one(unsigned long asid, unsigned long page) jump_to_uncached(); __raw_writel(page, MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT); __raw_writel(asid, MMU_UTLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT); + __raw_writel(page, MMU_ITLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT); + __raw_writel(asid, MMU_ITLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT); back_to_cached(); } |