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| author | Catalin Marinas <catalin.marinas@arm.com> | 2007-05-09 09:50:23 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2007-05-09 09:50:23 +0100 |
| commit | 065cf519c32984b7a78777aae3859baf5f5fd3d3 (patch) | |
| tree | a6d0fe57cfacb76bd90189101977ec8e6bab3ec0 /arch | |
| parent | 56163fcf194fb688fcf3cefa9b90c5ad41f74059 (diff) | |
| download | kernel_samsung_crespo-065cf519c32984b7a78777aae3859baf5f5fd3d3.zip kernel_samsung_crespo-065cf519c32984b7a78777aae3859baf5f5fd3d3.tar.gz kernel_samsung_crespo-065cf519c32984b7a78777aae3859baf5f5fd3d3.tar.bz2 | |
[ARM] armv7: add support for asid-tagged VIVT I-cache
ARMv7 can have VIPT, PIPT or ASID-tagged VIVT I-cache. This patch
adds the necessary invalidation of the I-cache when the ASID numbers
are re-used.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mm/context.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c index 9da43a0..c9e9a55 100644 --- a/arch/arm/mm/context.c +++ b/arch/arm/mm/context.c @@ -47,6 +47,13 @@ void __new_context(struct mm_struct *mm) : "r" (0)); isb(); flush_tlb_all(); + if (icache_is_vivt_asid_tagged()) { + asm("mcr p15, 0, %0, c7, c5, 0 @ invalidate I-cache\n" + "mcr p15, 0, %0, c7, c5, 6 @ flush BTAC/BTB\n" + : + : "r" (0)); + dsb(); + } } mm->context.id = asid; |