S5PC110: HERRING: Add machine files for FIMD

Signed-off-by: Janghyuck Kim <janghyuck.kim@samsung.com>

5 files changed, 486 insertions, 1 deletions

diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 1353657..b09f724 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -186,4 +186,10 @@ config MACH_S5PC110_CRESPO
 	  Machine support for Samsung CRESPO
 	  S5PC110(MCP) is one of package option of S5PV210
 
+config S5PV210_SETUP_FB
+	bool
+	depends on FB_S3C
+	default y
+	help
+	  Common setup code for FIMD controller.
 endif
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index c2d03ae..abd4975 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -31,7 +31,7 @@ obj-$(CONFIG_MACH_S5PC110_CRESPO)	+= mach-herring.o
 obj-y				+= dev-audio.o
 obj-$(CONFIG_S3C64XX_DEV_SPI)	+= dev-spi.o
 
-obj-$(CONFIG_S5PV210_SETUP_FB_24BPP)	+= setup-fb-24bpp.o
+obj-$(CONFIG_S5PV210_SETUP_FB)		+= setup-fb.o
 obj-$(CONFIG_S5PV210_SETUP_FIMC)	+= setup-fimc.o
 obj-$(CONFIG_S5PV210_SETUP_I2C1) 	+= setup-i2c1.o
 obj-$(CONFIG_S5PV210_SETUP_I2C2) 	+= setup-i2c2.o
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
index 32f3046..c4657d7 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -75,6 +75,11 @@
 #define S5PV210_PA_DMC0			0xF0000000
 #define S5PV210_PA_DMC1			0xF1400000
 
+#define S5PV210_PA_LCD	   	(0xF8000000)
+#define S5P_PA_LCD		S5PV210_PA_LCD
+#define S5PV210_SZ_LCD		SZ_1M
+#define S5P_SZ_LCD		S5PV210_SZ_LCD
+
 #define S5PV210_PA_VIC0			0xF2000000
 #define S5PV210_PA_VIC1			0xF2100000
 #define S5PV210_PA_VIC2			0xF2200000
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-gpio.h b/arch/arm/mach-s5pv210/include/mach/regs-gpio.h
index de0c899..5c786a9 100644
--- a/arch/arm/mach-s5pv210/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s5pv210/include/mach/regs-gpio.h
@@ -15,6 +15,225 @@
 
 #include <mach/map.h>
 
+/* Base addresses for each of the banks */
+
+#define S5PV210_GPA0_BASE		(S5P_VA_GPIO + 0x000)
+#define S5PV210_GPA1_BASE		(S5P_VA_GPIO + 0x020)
+#define S5PV210_GPB_BASE 		(S5P_VA_GPIO + 0x040)
+#define S5PV210_GPC0_BASE		(S5P_VA_GPIO + 0x060)
+#define S5PV210_GPC1_BASE		(S5P_VA_GPIO + 0x080)
+#define S5PV210_GPD0_BASE		(S5P_VA_GPIO + 0x0A0)
+#define S5PV210_GPD1_BASE		(S5P_VA_GPIO + 0x0C0)
+#define S5PV210_GPE0_BASE		(S5P_VA_GPIO + 0x0E0)
+#define S5PV210_GPE1_BASE		(S5P_VA_GPIO + 0x100)
+#define S5PV210_GPF0_BASE		(S5P_VA_GPIO + 0x120)
+#define S5PV210_GPF1_BASE		(S5P_VA_GPIO + 0x140)
+#define S5PV210_GPF2_BASE		(S5P_VA_GPIO + 0x160)
+#define S5PV210_GPF3_BASE		(S5P_VA_GPIO + 0x180)
+#define S5PV210_GPG0_BASE		(S5P_VA_GPIO + 0x1A0)
+#define S5PV210_GPG1_BASE		(S5P_VA_GPIO + 0x1C0d)
+#define S5PV210_GPG2_BASE		(S5P_VA_GPIO + 0x1E0)
+#define S5PV210_GPG3_BASE		(S5P_VA_GPIO + 0x200)
+#define S5PV210_GPH0_BASE		(S5P_VA_GPIO + 0xC00)
+#define S5PV210_GPH1_BASE		(S5P_VA_GPIO + 0xC20)
+#define S5PV210_GPH2_BASE		(S5P_VA_GPIO + 0xC40)
+#define S5PV210_GPH3_BASE		(S5P_VA_GPIO + 0xC60)
+#define S5PV210_GPI_BASE 		(S5P_VA_GPIO + 0x220)
+#define S5PV210_GPJ0_BASE		(S5P_VA_GPIO + 0x240)
+#define S5PV210_GPJ1_BASE		(S5P_VA_GPIO + 0x260)
+#define S5PV210_GPJ2_BASE		(S5P_VA_GPIO + 0x280)
+#define S5PV210_GPJ3_BASE		(S5P_VA_GPIO + 0x2A0)
+#define S5PV210_GPJ4_BASE		(S5P_VA_GPIO + 0x2C0)
+#define S5PV210_MP01_BASE		(S5P_VA_GPIO + 0x2E0)
+#define S5PV210_MP02_BASE		(S5P_VA_GPIO + 0x300)
+#define S5PV210_MP03_BASE		(S5P_VA_GPIO + 0x320)
+#define S5PV210_MP04_BASE		(S5P_VA_GPIO + 0x340)
+#define S5PV210_MP05_BASE		(S5P_VA_GPIO + 0x360)
+#define S5PV210_MP06_BASE		(S5P_VA_GPIO + 0x380)
+#define S5PV210_MP07_BASE		(S5P_VA_GPIO + 0x3A0)
+#define S5PV210_MP10_BASE		(S5P_VA_GPIO + 0x3C0)
+#define S5PV210_MP11_BASE		(S5P_VA_GPIO + 0x3E0)
+#define S5PV210_MP12_BASE		(S5P_VA_GPIO + 0x400)
+#define S5PV210_MP13_BASE		(S5P_VA_GPIO + 0x420)
+#define S5PV210_MP14_BASE		(S5P_VA_GPIO + 0x440)
+#define S5PV210_MP15_BASE		(S5P_VA_GPIO + 0x460)
+#define S5PV210_MP16_BASE		(S5P_VA_GPIO + 0x480)
+#define S5PV210_MP17_BASE		(S5P_VA_GPIO + 0x4A0)
+#define S5PV210_MP18_BASE		(S5P_VA_GPIO + 0x4C0)
+#define S5PV210_MP20_BASE		(S5P_VA_GPIO + 0x4E0)
+#define S5PV210_MP21_BASE		(S5P_VA_GPIO + 0x500)
+#define S5PV210_MP22_BASE		(S5P_VA_GPIO + 0x520)
+#define S5PV210_MP23_BASE		(S5P_VA_GPIO + 0x540)
+#define S5PV210_MP24_BASE		(S5P_VA_GPIO + 0x560)
+#define S5PV210_MP25_BASE		(S5P_VA_GPIO + 0x580)
+#define S5PV210_MP26_BASE		(S5P_VA_GPIO + 0x5A0)
+#define S5PV210_MP27_BASE		(S5P_VA_GPIO + 0x5C0)
+#define S5PV210_MP28_BASE		(S5P_VA_GPIO + 0x5E0)
+#define S5PV210_ETC0_BASE		(S5P_VA_GPIO + 0x600)
+#define S5PV210_ETC1_BASE		(S5P_VA_GPIO + 0x620)
+#define S5PV210_ETC2_BASE		(S5P_VA_GPIO + 0x640)
+#define S5PV210_ETC4_BASE		(S5P_VA_GPIO + 0x660)
+
+#define S5PV210_GPA0_INT_CON		(S5P_VA_GPIO + 0x700)
+#define S5PV210_GPA0_INTFLTCON0		(S5P_VA_GPIO + 0x800)
+#define S5PV210_GPA0_INTFLTCON1		(S5P_VA_GPIO + 0x804)
+#define S5PV210_GPA0_INT_MASK		(S5P_VA_GPIO + 0x900)
+#define S5PV210_GPA0_INT_PEND		(S5P_VA_GPIO + 0xA00)
+#define S5PV210_GPA0_INT_FIXPRI		(S5P_VA_GPIO + 0xB14)
+
+#define S5PV210_GPA1_INT_CON		(S5P_VA_GPIO + 0x704)
+#define S5PV210_GPA1_INTFLTCON0		(S5P_VA_GPIO + 0x808)
+#define S5PV210_GPA1_INTFLTCON1		(S5P_VA_GPIO + 0x80C)
+#define S5PV210_GPA1_INT_MASK		(S5P_VA_GPIO + 0x904)
+#define S5PV210_GPA1_INT_PEND		(S5P_VA_GPIO + 0xA04)
+#define S5PV210_GPA1_INT_FIXPRI		(S5P_VA_GPIO + 0xB18)
+
+#define S5PV210_GPB_INT_CON		(S5P_VA_GPIO + 0x708)
+#define S5PV210_GPB_INTFLTCON0		(S5P_VA_GPIO + 0x810)
+#define S5PV210_GPB_INTFLTCON1		(S5P_VA_GPIO + 0x814)
+#define S5PV210_GPB_INT_MASK		(S5P_VA_GPIO + 0x908)
+#define S5PV210_GPB_INT_PEND		(S5P_VA_GPIO + 0xA08)
+#define S5PV210_GPB_INT_FIXPRI		(S5P_VA_GPIO + 0xB1C)
+
+#define S5PV210_GPC0_INT_CON		(S5P_VA_GPIO + 0x70C)
+#define S5PV210_GPC0_INTFLTCON0		(S5P_VA_GPIO + 0x818)
+#define S5PV210_GPC0_INTFLTCON1		(S5P_VA_GPIO + 0x81C)
+#define S5PV210_GPC0_INT_MASK		(S5P_VA_GPIO + 0x90C)
+#define S5PV210_GPC0_INT_PEND		(S5P_VA_GPIO + 0xA0C)
+#define S5PV210_GPC0_INT_FIXPRI		(S5P_VA_GPIO + 0xB20)
+
+#define S5PV210_GPC1_INT_CON		(S5P_VA_GPIO + 0x710)
+#define S5PV210_GPC1_INTFLTCON0		(S5P_VA_GPIO + 0x820)
+#define S5PV210_GPC1_INTFLTCON1		(S5P_VA_GPIO + 0x824)
+#define S5PV210_GPC1_INT_MASK		(S5P_VA_GPIO + 0x910)
+#define S5PV210_GPC1_INT_PEND		(S5P_VA_GPIO + 0xA10)
+#define S5PV210_GPC1_INT_FIXPRI		(S5P_VA_GPIO + 0xB24)
+
+#define S5PV210_GPD0_INT_CON		(S5P_VA_GPIO + 0x714)
+#define S5PV210_GPD0_INTFLTCON0		(S5P_VA_GPIO + 0x828)
+#define S5PV210_GPD0_INTFLTCON1		(S5P_VA_GPIO + 0x82C)
+#define S5PV210_GPD0_INT_MASK		(S5P_VA_GPIO + 0x914)
+#define S5PV210_GPD0_INT_PEND		(S5P_VA_GPIO + 0xA14)
+#define S5PV210_GPD0_INT_FIXPRI		(S5P_VA_GPIO + 0xB28)
+
+#define S5PV210_GPD1_INT_CON		(S5P_VA_GPIO + 0x718)
+#define S5PV210_GPD1_INTFLTCON0		(S5P_VA_GPIO + 0x830)
+#define S5PV210_GPD1_INTFLTCON1		(S5P_VA_GPIO + 0x834)
+#define S5PV210_GPD1_INT_MASK		(S5P_VA_GPIO + 0x918)
+#define S5PV210_GPD1_INT_PEND		(S5P_VA_GPIO + 0xA18)
+#define S5PV210_GPD1_INT_FIXPRI		(S5P_VA_GPIO + 0xB2C)
+
+#define S5PV210_GPE0_INT_CON		(S5P_VA_GPIO + 0x71C)
+#define S5PV210_GPE0_INTFLTCON0		(S5P_VA_GPIO + 0x838)
+#define S5PV210_GPE0_INTFLTCON1		(S5P_VA_GPIO + 0x83C)
+#define S5PV210_GPE0_INT_MASK		(S5P_VA_GPIO + 0x91C)
+#define S5PV210_GPE0_INT_PEND		(S5P_VA_GPIO + 0xA1C)
+#define S5PV210_GPE0_INT_FIXPRI		(S5P_VA_GPIO + 0xB30)
+
+#define S5PV210_GPE1_INT_CON		(S5P_VA_GPIO + 0x720)
+#define S5PV210_GPE1_INTFLTCON0		(S5P_VA_GPIO + 0x840)
+#define S5PV210_GPE1_INTFLTCON1		(S5P_VA_GPIO + 0x844)
+#define S5PV210_GPE1_INT_MASK		(S5P_VA_GPIO + 0x920)
+#define S5PV210_GPE1_INT_PEND		(S5P_VA_GPIO + 0xA20)
+#define S5PV210_GPE1_INT_FIXPRI		(S5P_VA_GPIO + 0xB34)
+
+#define S5PV210_GPF0_INT_CON		(S5P_VA_GPIO + 0x724)
+#define S5PV210_GPF0_INTFLTCON0		(S5P_VA_GPIO + 0x848)
+#define S5PV210_GPF0_INTFLTCON1		(S5P_VA_GPIO + 0x84C)
+#define S5PV210_GPF0_INT_MASK		(S5P_VA_GPIO + 0x924)
+#define S5PV210_GPF0_INT_PEND		(S5P_VA_GPIO + 0xA24)
+#define S5PV210_GPF0_INT_FIXPRI		(S5P_VA_GPIO + 0xB38)
+
+#define S5PV210_GPF1_INT_CON		(S5P_VA_GPIO + 0x728)
+#define S5PV210_GPF1_INTFLTCON0		(S5P_VA_GPIO + 0x850)
+#define S5PV210_GPF1_INTFLTCON1		(S5P_VA_GPIO + 0x854)
+#define S5PV210_GPF1_INT_MASK		(S5P_VA_GPIO + 0x928)
+#define S5PV210_GPF1_INT_PEND		(S5P_VA_GPIO + 0xA28)
+#define S5PV210_GPF1_INT_FIXPRI		(S5P_VA_GPIO + 0xB3C)
+
+#define S5PV210_GPF2_INT_CON		(S5P_VA_GPIO + 0x72C)
+#define S5PV210_GPF2_INTFLTCON0		(S5P_VA_GPIO + 0x858)
+#define S5PV210_GPF2_INTFLTCON1		(S5P_VA_GPIO + 0x85C)
+#define S5PV210_GPF2_INT_MASK		(S5P_VA_GPIO + 0x92C)
+#define S5PV210_GPF2_INT_PEND		(S5P_VA_GPIO + 0xA2C)
+#define S5PV210_GPF2_INT_FIXPRI		(S5P_VA_GPIO + 0xB40)
+
+#define S5PV210_GPF3_INT_CON		(S5P_VA_GPIO + 0x730)
+#define S5PV210_GPF3_INTFLTCON0		(S5P_VA_GPIO + 0x860)
+#define S5PV210_GPF3_INTFLTCON1		(S5P_VA_GPIO + 0x864)
+#define S5PV210_GPF3_INT_MASK		(S5P_VA_GPIO + 0x930)
+#define S5PV210_GPF3_INT_PEND		(S5P_VA_GPIO + 0xA30)
+#define S5PV210_GPF3_INT_FIXPRI		(S5P_VA_GPIO + 0xB44)
+
+#define S5PV210_GPG0_INT_CON		(S5P_VA_GPIO + 0x734)
+#define S5PV210_GPG0_INTFLTCON0		(S5P_VA_GPIO + 0x868)
+#define S5PV210_GPG0_INTFLTCON1		(S5P_VA_GPIO + 0x86C)
+#define S5PV210_GPG0_INT_MASK		(S5P_VA_GPIO + 0x934)
+#define S5PV210_GPG0_INT_PEND		(S5P_VA_GPIO + 0xA34)
+#define S5PV210_GPG0_INT_FIXPRI		(S5P_VA_GPIO + 0xB48)
+
+#define S5PV210_GPG1_INT_CON		(S5P_VA_GPIO + 0x738)
+#define S5PV210_GPG1_INTFLTCON0		(S5P_VA_GPIO + 0x870)
+#define S5PV210_GPG1_INTFLTCON1		(S5P_VA_GPIO + 0x874)
+#define S5PV210_GPG1_INT_MASK		(S5P_VA_GPIO + 0x938)
+#define S5PV210_GPG1_INT_PEND		(S5P_VA_GPIO + 0xA38)
+#define S5PV210_GPG1_INT_FIXPRI		(S5P_VA_GPIO + 0xB4C)
+
+#define S5PV210_GPG2_INT_CON		(S5P_VA_GPIO + 0x73C)
+#define S5PV210_GPG2_INTFLTCON0		(S5P_VA_GPIO + 0x878)
+#define S5PV210_GPG2_INTFLTCON1		(S5P_VA_GPIO + 0x87C)
+#define S5PV210_GPG2_INT_MASK		(S5P_VA_GPIO + 0x93C)
+#define S5PV210_GPG2_INT_PEND		(S5P_VA_GPIO + 0xA3C)
+#define S5PV210_GPG2_INT_FIXPRI		(S5P_VA_GPIO + 0xB50)
+
+#define S5PV210_GPG3_INT_CON		(S5P_VA_GPIO + 0x740)
+#define S5PV210_GPG3_INTFLTCON0		(S5P_VA_GPIO + 0x880)
+#define S5PV210_GPG3_INTFLTCON1		(S5P_VA_GPIO + 0x884)
+#define S5PV210_GPG3_INT_MASK		(S5P_VA_GPIO + 0x940)
+#define S5PV210_GPG3_INT_PEND		(S5P_VA_GPIO + 0xA40)
+#define S5PV210_GPG3_INT_FIXPRI		(S5P_VA_GPIO + 0xB54)
+
+#define S5PV210_GPJ0_INT_CON		(S5P_VA_GPIO + 0x744)
+#define S5PV210_GPJ0_INTFLTCON0		(S5P_VA_GPIO + 0x888)
+#define S5PV210_GPJ0_INTFLTCON1		(S5P_VA_GPIO + 0x88C)
+#define S5PV210_GPJ0_INT_MASK		(S5P_VA_GPIO + 0x944)
+#define S5PV210_GPJ0_INT_PEND		(S5P_VA_GPIO + 0xA44)
+#define S5PV210_GPJ0_INT_FIXPRI		(S5P_VA_GPIO + 0xB58)
+
+#define S5PV210_GPJ1_INT_CON		(S5P_VA_GPIO + 0x748)
+#define S5PV210_GPJ1_INTFLTCON0		(S5P_VA_GPIO + 0x890)
+#define S5PV210_GPJ1_INTFLTCON1		(S5P_VA_GPIO + 0x894)
+#define S5PV210_GPJ1_INT_MASK		(S5P_VA_GPIO + 0x948)
+#define S5PV210_GPJ1_INT_PEND		(S5P_VA_GPIO + 0xA48)
+#define S5PV210_GPJ1_INT_FIXPRI		(S5P_VA_GPIO + 0xB5C)
+
+#define S5PV210_GPJ2_INT_CON		(S5P_VA_GPIO + 0x74C)
+#define S5PV210_GPJ2_INTFLTCON0		(S5P_VA_GPIO + 0x898)
+#define S5PV210_GPJ2_INTFLTCON1		(S5P_VA_GPIO + 0x89C)
+#define S5PV210_GPJ2_INT_MASK		(S5P_VA_GPIO + 0x94C)
+#define S5PV210_GPJ2_INT_PEND		(S5P_VA_GPIO + 0xA4C)
+#define S5PV210_GPJ2_INT_FIXPRI		(S5P_VA_GPIO + 0xB60)
+
+#define S5PV210_GPJ3_INT_CON		(S5P_VA_GPIO + 0x750)
+#define S5PV210_GPJ3_INTFLTCON0		(S5P_VA_GPIO + 0x8A0)
+#define S5PV210_GPJ3_INTFLTCON1		(S5P_VA_GPIO + 0x8A4)
+#define S5PV210_GPJ3_INT_MASK		(S5P_VA_GPIO + 0x950)
+#define S5PV210_GPJ3_INT_PEND		(S5P_VA_GPIO + 0xA50)
+#define S5PV210_GPJ3_INT_FIXPRI		(S5P_VA_GPIO + 0xB64)
+
+#define S5PV210_GPJ4_INT_CON		(S5P_VA_GPIO + 0x754)
+#define S5PV210_GPJ4_INTFLTCON0		(S5P_VA_GPIO + 0x8A8)
+#define S5PV210_GPJ4_INTFLTCON1		(S5P_VA_GPIO + 0x8AC)
+#define S5PV210_GPJ4_INT_MASK		(S5P_VA_GPIO + 0x954)
+#define S5PV210_GPJ4_INT_PEND		(S5P_VA_GPIO + 0xA54)
+#define S5PV210_GPJ4_INT_FIXPRI		(S5P_VA_GPIO + 0xB68)
+
+#define S5PV210_EXT_INT_GRPPRI		(S5P_VA_GPIO + 0xB00)
+#define S5PV210_EXT_INT_PRIO		(S5P_VA_GPIO + 0xB04)
+#define S5PV210_EXT_INT_SVC		(S5P_VA_GPIO + 0xB08)
+#define S5PV210_EXT_INT_SVC_PND		(S5P_VA_GPIO + 0xB0C)
+#define S5PV210_EXT_INT_GRPFIXPRI	(S5P_VA_GPIO + 0xB10)
+
 #define S5PV210_EINT30CON		(S5P_VA_GPIO + 0xE00)
 #define S5P_EINT_CON(x)			(S5PV210_EINT30CON + ((x) * 0x4))
 
diff --git a/arch/arm/mach-s5pv210/setup-fb.c b/arch/arm/mach-s5pv210/setup-fb.c
new file mode 100644
index 0000000..808cf42
--- /dev/null
+++ b/arch/arm/mach-s5pv210/setup-fb.c
@@ -0,0 +1,255 @@
+/* linux/arch/arm/mach-s5pv210/setup-fb.c
+ *
+ * Copyright (c) 2009 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * Base FIMD controller configuration
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+#include <plat/clock.h>
+#include <plat/gpio-cfg.h>
+#include <plat/fb.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-gpio.h>
+#include <linux/io.h>
+#include <mach/map.h>
+#include <mach/pd.h>
+#include <mach/gpio-bank.h>
+
+struct platform_device; /* don't need the contents */
+
+void s3cfb_cfg_gpio(struct platform_device *pdev)
+{
+	int i;
+
+	for (i = 0; i < 8; i++) {
+		s3c_gpio_cfgpin(S5PV210_GPF0(i), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(S5PV210_GPF0(i), S3C_GPIO_PULL_NONE);
+	}
+
+	for (i = 0; i < 8; i++) {
+		s3c_gpio_cfgpin(S5PV210_GPF1(i), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(S5PV210_GPF1(i), S3C_GPIO_PULL_NONE);
+	}
+
+	for (i = 0; i < 8; i++) {
+		s3c_gpio_cfgpin(S5PV210_GPF2(i), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(S5PV210_GPF2(i), S3C_GPIO_PULL_NONE);
+	}
+
+	for (i = 0; i < 4; i++) {
+		s3c_gpio_cfgpin(S5PV210_GPF3(i), S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(S5PV210_GPF3(i), S3C_GPIO_PULL_NONE);
+	}
+
+	/* mDNIe SEL: why we shall write 0x2 ? */
+	writel(0x2, S5P_MDNIE_SEL);
+
+	/* drive strength to max */
+	writel(0xffffffff, S5PV210_GPF0_BASE + 0xc);
+	writel(0xffffffff, S5PV210_GPF1_BASE + 0xc);
+	writel(0xffffffff, S5PV210_GPF2_BASE + 0xc);
+	writel(0x000000ff, S5PV210_GPF3_BASE + 0xc);
+}
+
+int s3cfb_clk_on(struct platform_device *pdev, struct clk **s3cfb_clk)
+{
+	struct clk *sclk = NULL;
+	struct clk *mout_mpll = NULL;
+	struct clk *lcd = NULL;
+	u32 rate = 0;
+	int ret;
+
+	sclk = clk_get(&pdev->dev, "sclk_fimd");
+	if (IS_ERR(sclk)) {
+		dev_err(&pdev->dev, "failed to get sclk for fimd\n");
+		goto err_clk1;
+	}
+
+	mout_mpll = clk_get(&pdev->dev, "mout_mpll");
+	if (IS_ERR(mout_mpll)) {
+		dev_err(&pdev->dev, "failed to get mout_mpll\n");
+		goto err_clk1;
+	}
+
+	clk_set_parent(sclk, mout_mpll);
+
+	//rate = clk_round_rate(sclk, 166750000);
+	//dev_dbg(&pdev->dev, "set fimd sclk rate to %d\n", rate);
+
+	if (!rate)
+		rate = 166750000;
+
+	clk_set_rate(sclk, rate);
+	dev_dbg(&pdev->dev, "set fimd sclk rate to %d\n", rate);
+
+	clk_put(mout_mpll);
+
+	ret = s5pv210_pd_enable("fimd_pd");
+	if (ret < 0) {
+		dev_err(&pdev->dev, "failed to enable fimd power domain\n");
+		goto err_clk2;
+	}
+
+	clk_enable(sclk);
+
+	lcd = clk_get(&pdev->dev, "lcd");
+	if (IS_ERR(lcd)) {
+		dev_err(&pdev->dev, "failed to get IP clock for fimd\n");
+		goto err_clk2;
+	}
+
+	clk_enable(lcd);
+
+	*s3cfb_clk = sclk;
+
+	return 0;
+
+err_clk2:
+	clk_put(mout_mpll);
+
+err_clk1:
+	clk_put(sclk);
+
+	return -EINVAL;
+}
+
+int s3cfb_clk_off(struct platform_device *pdev, struct clk **clk)
+{
+	int ret;
+
+	clk_disable(*clk);
+	clk_put(*clk);
+
+	*clk = NULL;
+	ret = s5pv210_pd_disable("fimd_pd");
+	if (ret < 0)
+		dev_err(&pdev->dev, "failed to disable fimd power domain\n");
+
+	return 0;
+}
+
+void s3cfb_get_clk_name(char *clk_name)
+{
+	strcpy(clk_name, "sclk_fimd");
+}
+#ifdef CONFIG_FB_S3C_LTE480WV
+int s3cfb_backlight_onoff(struct platform_device *pdev, int onoff)
+{
+	int err;
+
+	err = gpio_request(S5PV210_GPD0(3), "GPD0");
+
+	if (err) {
+		printk(KERN_ERR "failed to request GPD0 for "
+			"lcd backlight control\n");
+		return err;
+	}
+
+	if (onoff) {
+		gpio_direction_output(S5PV210_GPD0(3), 1);
+		/* 2009.12.28 by icarus : added for PWM backlight */
+		s3c_gpio_cfgpin(S5PV210_GPD0(3), S5PV210_GPD_0_3_TOUT_3);
+
+	}
+	else {
+		gpio_direction_output(S5PV210_GPD0(3), 0);
+	}
+	gpio_free(S5PV210_GPD0(3));
+	return 0;
+}
+
+int s3cfb_reset_lcd(struct platform_device *pdev)
+{
+	int err;
+
+	err = gpio_request(S5PV210_GPH0(6), "GPH0");
+	if (err) {
+		printk(KERN_ERR "failed to request GPH0 for "
+			"lcd reset control\n");
+		return err;
+	}
+
+	gpio_direction_output(S5PV210_GPH0(6), 1);
+	mdelay(100);
+
+	gpio_set_value(S5PV210_GPH0(6), 0);
+	mdelay(10);
+
+	gpio_set_value(S5PV210_GPH0(6), 1);
+	mdelay(10);
+
+	gpio_free(S5PV210_GPH0(6));
+
+	return 0;
+}
+#elif defined(CONFIG_FB_S3C_HT101HD1)
+int s3cfb_backlight_on(struct platform_device *pdev)
+{
+	int err;
+
+	err = gpio_request(S5PV210_GPB(2), "GPB");
+	if (err) {
+		printk(KERN_ERR "failed to request GPB for "
+			"lcd backlight control\n");
+		return err;
+	}
+
+#ifdef CONFIG_TYPE_PROTO3
+	err = gpio_request(S5PV210_GPD0(1), "GPD0");
+	if (err) {
+		printk(KERN_ERR "failed to request GPD0 for "
+			"lcd backlight control\n");
+		return err;
+	}
+#endif
+
+	gpio_direction_output(S5PV210_GPB(2), 1); /* LED_EN (SPI1_MOSI) */
+
+#ifdef CONFIG_TYPE_PROTO3
+	/* LCD_PWR_EN is only for Proto3 */
+	gpio_direction_output(S5PV210_GPD0(1), 1);
+	mdelay(10);
+#endif
+
+	gpio_free(S5PV210_GPB(2));
+#ifdef CONFIG_TYPE_PROTO3
+	gpio_free(S5PV210_GPD0(1));
+#endif
+
+	return 0;
+}
+
+int s3cfb_reset_lcd(struct platform_device *pdev)
+{
+	int err;
+
+	err = gpio_request(S5PV210_GPH0(1), "GPH0");
+	if (err) {
+		printk(KERN_ERR "failed to request GPH0 for "
+			"lcd reset control\n");
+		return err;
+	}
+
+	gpio_direction_output(S5PV210_GPH0(1), 1);
+
+	gpio_set_value(S5PV210_GPH0(1), 0);
+
+	gpio_set_value(S5PV210_GPH0(1), 1);
+
+	gpio_free(S5PV210_GPH0(1));
+
+	return 0;
+}
+#endif