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| author | David Mosberger-Tang <davidm@hpl.hp.com> | 2005-04-27 21:22:08 -0700 |
|---|---|---|
| committer | Tony Luck <tony.luck@intel.com> | 2005-04-27 21:22:08 -0700 |
| commit | e7e965fa1961a8ce32cbbb1bd436c655ad03973e (patch) | |
| tree | fce517f87be25a0e49d62adb56460a4e7ee36716 /arch | |
| parent | fbf7192ba06e4b55022231e5fdb9db8ce3ad6307 (diff) | |
| download | kernel_samsung_crespo-e7e965fa1961a8ce32cbbb1bd436c655ad03973e.zip kernel_samsung_crespo-e7e965fa1961a8ce32cbbb1bd436c655ad03973e.tar.gz kernel_samsung_crespo-e7e965fa1961a8ce32cbbb1bd436c655ad03973e.tar.bz2 | |
[IA64] use srlz.d instead of srlz.i in ia64_leave_kernel()
This patch switches the srlz.i in ia64_leave_kernel() to srlz.d. As
per architecture manual, the former is needed only to ensure that the
clearing of PSR.IC is seen by the VHPT for subsequent instruction
fetches. However, since the remainder of the code (up to and
including the RFI instruction) is mapped by a pinned TLB entry, there
is no chance of an iTLB miss and we don't care whether or not the VHPT
sees PSR.IC cleared. Since srlz.d is substantially cheaper than
srlz.i, this should shave off a few cycles off the interrupt path
(unverified though; I'm not setup to measure this at the moment).
Signed-off-by: David Mosberger-Tang <davidm@hpl.hp.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/ia64/kernel/entry.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/ia64/kernel/entry.S b/arch/ia64/kernel/entry.S index a7542c3..4517d4a 100644 --- a/arch/ia64/kernel/entry.S +++ b/arch/ia64/kernel/entry.S @@ -880,7 +880,7 @@ GLOBAL_ENTRY(ia64_leave_kernel) ldf.fill f7=[r2],PT(F11)-PT(F7) ldf.fill f8=[r3],32 ;; - srlz.i // ensure interruption collection is off + srlz.d // ensure that inter. collection is off (VHPT is don't care, since text is pinned) mov ar.ccv=r15 ;; ldf.fill f11=[r2] |