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| author | Juha Yrjola <juha.yrjola@solidboot.com> | 2006-09-25 12:41:37 +0300 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2006-09-25 12:41:37 +0300 |
| commit | eaca33df44c0d00bc12b16e72b728ade25adf14d (patch) | |
| tree | e825e325d2b398cd14bccb1ed77a3007c63bd888 /arch | |
| parent | dbab288be47ddc84ad52ff926ea1a0efd33acb57 (diff) | |
| download | kernel_samsung_crespo-eaca33df44c0d00bc12b16e72b728ade25adf14d.zip kernel_samsung_crespo-eaca33df44c0d00bc12b16e72b728ade25adf14d.tar.gz kernel_samsung_crespo-eaca33df44c0d00bc12b16e72b728ade25adf14d.tar.bz2 | |
ARM: OMAP: Add write memory barriers to OMAP2 clock code
After adjusting clock parameters, OMAP2 CPUs need a memory
barrier to make sure the changes go into effect immediately.
Otherwise bad things will happen if we try to access the
peripheral whose clock is just being enabled.
Signed-off-by: Juha Yrjola <juha.yrjola@solidboot.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-omap2/clock.c | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 82643a2..302d5a7 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -135,6 +135,7 @@ static int _omap2_clk_enable(struct clk * clk) regval32 = __raw_readl(clk->enable_reg); regval32 |= (1 << clk->enable_bit); __raw_writel(regval32, clk->enable_reg); + wmb(); return 0; } @@ -168,6 +169,7 @@ static void _omap2_clk_disable(struct clk *clk) regval32 = __raw_readl(clk->enable_reg); regval32 &= ~(1 << clk->enable_bit); __raw_writel(regval32, clk->enable_reg); + wmb(); } static int omap2_clk_enable(struct clk *clk) @@ -697,12 +699,14 @@ static int omap2_clk_set_rate(struct clk *clk, unsigned long rate) reg_val = __raw_readl(reg); reg_val &= ~(field_mask << div_off); reg_val |= (field_val << div_off); - __raw_writel(reg_val, reg); + wmb(); clk->rate = clk->parent->rate / field_val; - if (clk->flags & DELAYED_APP) + if (clk->flags & DELAYED_APP) { __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL); + wmb(); + } ret = 0; } else if (clk->set_rate != 0) ret = clk->set_rate(clk, rate); @@ -838,10 +842,12 @@ static int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) reg_val = __raw_readl(reg) & ~(field_mask << src_off); reg_val |= (field_val << src_off); __raw_writel(reg_val, reg); + wmb(); - if (clk->flags & DELAYED_APP) + if (clk->flags & DELAYED_APP) { __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL); - + wmb(); + } if (clk->usecount > 0) _omap2_clk_enable(clk); |