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| author | Yuanhan Liu <yuanhan.liu@linux.intel.com> | 2010-12-15 15:42:31 +0800 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2010-12-15 11:16:57 +0000 |
| commit | 1398261a2e84c537c409259cfe9db3d0abcd9f99 (patch) | |
| tree | bbf7e6a450d83775b093b5a50e976a230e46fdd3 /drivers/gpu/drm/i915/i915_debugfs.c | |
| parent | b7f1de289c50beb4998611ba5373e539efd0f79f (diff) | |
| download | kernel_samsung_crespo-1398261a2e84c537c409259cfe9db3d0abcd9f99.zip kernel_samsung_crespo-1398261a2e84c537c409259cfe9db3d0abcd9f99.tar.gz kernel_samsung_crespo-1398261a2e84c537c409259cfe9db3d0abcd9f99.tar.bz2 | |
drm/i915: Add self-refresh support on Sandybridge
Add the support of memory self-refresh on Sandybridge, which is now
support 3 levels of watermarks and the source of the latency values
for watermarks has changed.
On Sandybridge, the LP0 WM value is not hardcoded any more. All the
latency value is now should be extracted from MCHBAR SSKPD register.
And the MCHBAR base address is changed, too.
For the WM values, if any calculated watermark values is larger than
the maximum value that can be programmed into the associated watermark
register, that watermark must be disabled.
Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
[ickle: remove duplicate compute routines and fixup for checkpatch]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_debugfs.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_debugfs.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 2282199..864e75d 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -933,7 +933,7 @@ static int i915_sr_status(struct seq_file *m, void *unused) drm_i915_private_t *dev_priv = dev->dev_private; bool sr_enabled = false; - if (IS_GEN5(dev)) + if (HAS_PCH_SPLIT(dev)) sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev)) sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |