gpu: pvr: Update to DDK 1.6.16.4046

Change-Id: If38412971f275715a47bf200aeebe1139d2620f8

gpu: pvr: Update DDK version number to 1.6.16.4061

This is a version number change only, which is required for
compatibility with the user-mode driver.

Change-Id: I4e0f59a8f98ea28f9c0862aff76c0bfa2710efe0

gpu: pvr: Update to DDK 1.6.16.4124

Change-Id: Ifbc47f2552f031e92e02b31a9715e3e42cf14b3c

gpu: pvr: Update DDK version number to 1.6.16.4131

This is a version number change only, which is required for
compatibility with the user-mode driver.

Change-Id: I8c4df3ae638ad2d358aa3977ffb7f6e9bdb1de4a

gpu: pvr: Update to DDK 1.7.17.4142

Signed-off-by: Simon Wilson <simonwilson@google.com>

gpu: pvr: Update to DDK 1.7.17.4474

Signed-off-by: Simon Wilson <simonwilson@google.com>

gpu: pvr: Update to DDK 1.8.18.380

gpu: pvr: Update to DDK 1.8.18.468

gpu: pvr: Update to DDK 1.8.18.684

Change-Id: I7a4e92add9f1c61862a06e51b68169d93b67a001
Signed-off-by: JP Abgrall <jpa@google.com>

gpu: pvr: Update to DDK 1.8.18.726

gpu: pvr: Update to DDK 1.8.18.749

gpu: pvr: Fix to compile on 2.6.39

Change-Id: I79c07b3a0ca219f7e6d8dec97f41adc3fc5a01ff
Signed-off-by: Arve Hjønnevåg <arve@android.com>

gpu: pvr: Update to DDK 1.8.18.834

Fix a couple of double frees in PVRSRVSwapToDCBuffer2KM. Fixes for
various ION client refcounting issues.

gpu: pvr: Update to DDK 1.8.18.844

Various fixes to prevent arbitrary memory corruption with ION:

 * Remove the per-process ION client - there is now just one "kernel"
   ION client
 * Ensure that the mmap mutex is taken before walking the offset
   struct list
 * Implement ION cache flush code

gpu: pvr: Update to DDK 1.8.18.853

Change-Id: I5e2e1619aae0634ca5036c5ab60e1e4339a35b0d

gpu: pvr: Update to DDK 1.8.18.866

Change-Id: I91548bf62aa30ff41814118a3a6d49303fc16bfc

gpu: pvr: Update to DDK 1.8.18.877

Change-Id: Id87c6318a7705ad51e5bfd487a9b216f373c0caf

gpu: pvr: Update to DDK 1.8.18.891

This is a version number change only, which is required for
compatibility with the user-mode driver.

Change-Id: I30b11a79973179d7dcb0923d2106a1f072b88a77

gpu: pvr: Update to DDK 1.8.18.919

- Bump CONFIG_FB_S3C_NR_BUFFERS to 6, to increase the display carveout
  size by 3MB. This is to make space for video-decode buffers.

- drivers/gpu/pvr Makefile cleanups. Remove dead build options.

- Groundwork for "multiple readers" capability required by HWC.

- Merge s3c_lcd and s5pc110 display and system code with latest
  versions. Add video-decode carveout capability.

Change-Id: I8836204451eebf12b030404177cfd6bc4b294489

gpu: pvr: Update to DDK 1.8.18.927

 - More work on "multiple reader" capability for HWC.

Change-Id: I0fd372b03de5bb86591d4b2be208be3749670248

gpu: pvr: Update to DDK 1.8.18.943

Change-Id: Iae3d13fc82dfa0cffc6bce98a056f1b0d4b1f62a

gpu: pvr: Update to DDK 1.8.18.945

 - Add ProcessFlip V2 capability to s3c_displayclass.c.
 - Enables FIMC integration.

Change-Id: Ibc1dec9c24f5f55ce1436674b36571f3718b4e96

gpu: pvr: Update to DDK 1.8.18.964

 - Add SUPPORT_GET_DC_BUFFERS_SYS_PHYADDRS to enable returning
   of display buffer physical addresses to user-space.
   Required for C110 HWC. Not enabled on Prime.

Change-Id: I5f19c7b1cea193aaca24cceca518d0100171c823

gpu: pvr: Update to DDK 1.8@273945

This is a version number change only, which is required for
compatibility with the user-mode driver.

gpu: pvr: Update to DDK 1.8@274226

gpu: pvr: Update to DDK 1.8@274836

gpu: pvr: Update to DDK 1.8@275425

This is a version number change only, which is required for
compatibility with the user-mode driver.

gpu: pvr: Update to DDK 1.8@275540

 - Allow userspace to obtain a copy of the current kernel reference
   count of a MemInfo. Fixes a bug on crespo that allowed a Y/UV
   swapchain buffer to be incorrectly re-used in another allocation.

Change-Id: I6a10d75ad9efb4109b6bfa34b3478dc7b36caac2

gpu: pvr: Update to DDK 1.8@275916

gpu: pvr: Update to DDK 1.8@276629

Merged with upstream s3c_lcd.

gpu: pvr: Update to DDK 1.8@278427

 - Fix a possible livelock scenario in s3c_lcd, by scheduling the MISR
   in the vsync handler.

Change-Id: If5c57b8a8658159d2912d89074015bb03b3f5ed3

gpu: pvr: Update to DDK 1.8@279068

Also make it possible to build the debug (pdump) driver.

Change-Id: I90f9a5c566a9d6205e801302bfb4f881f53e3247

gpu: pvr: Update to DDK 1.8@288777

This is a version number change only, which is required for
compatibility with the user-mode driver.

Change-Id: Ia22454fd91e280cf35cf798806dfa2b9505d0018

gpu: pvr: Update to DDK 1.8@289037

 - Merge with upstream TILER allocation wrap support in preparation for
   video encoder integration.
 - Suppress some overly verbose kernel messages.
 - Remove incorrect/unnecssary VM_PFNMAP sanity check.

Change-Id: Ia30a3316e1c9d2dc421afa5068a977b25618c85d

gpu: pvr: Update to DDK 1.8@289270

This is a version number change only, which is required for
compatibility with the user-mode driver.

Change-Id: Ic827cd7f22792c900708e77b0af48d5824790581

gpu: pvr: Update to DDK 1.8@289794

This is a version number change only, which is required for
compatibility with the user-mode driver.

Change-Id: Iba07b4cb193d87000aacb0408993841b99c8cb3e

gpu: pvr: Update to DDK 1.8@291121

 - Merged TI heap configuration change
 - Pass ROC2 devvaddr through to userspace (better debug)

Change-Id: Ie43b9af490190adbe0d1e34119af392f1ea420f5

gpu: pvr: Update to DDK 1.8@292125

Change-Id: I2b6e31f950a7ea98ff4db4feb160886c3d6eab7c

gpu: pvr: Update to DDK 1.8@292423

Change-Id: I4086ba1f3f3a6e5f7e605b156d1e01151da17223

gpu: pvr: Update to DDK 1.8@293295

Change-Id: Iec7d62292583d6b8e0fa157aa32e3156090a529d

gpu: pvr: Update to DDK 1.8@295945

 - Make sure buffer IDs propagate to other process mappings.
   Debug feature only.

Change-Id: Id4b360b9e6b76951129791200d1df7e8d42708e9

gpu: pvr: Update to DDK 1.8@297401

 - Security fixes.
   Remove ability to map primary surface in any process.
   Hide user-accessible path to OSPanic().

Change-Id: Iff7d56b04400625cac6f1f6e123749bdaeb3908c

gpu: pvr: Update to DDK 1.8@298138

This is a version number change only, which is required for
compatibility with the user-mode driver.

Change-Id: I9edf13aaedf0b56c9922c63d84a2d99ec7b6aae3

gpu: pvr: Update to DDK 1.8@300406

This is a version number change only, which is required for
compatibility with the user-mode driver.

Change-Id: I6cde977c5cfdf13f7ef43e01f2c0dba1bc0659b6

1 files changed, 305 insertions, 145 deletions

diff --git a/drivers/gpu/pvr/sgx/sgxreset.c b/drivers/gpu/pvr/sgx/sgxreset.c
index 68d0e79..0baa11f 100644
--- a/drivers/gpu/pvr/sgx/sgxreset.c
+++ b/drivers/gpu/pvr/sgx/sgxreset.c
@@ -1,6 +1,6 @@
 /**********************************************************************
  *
- * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved.
+ * Copyright (C) Imagination Technologies Ltd. All rights reserved.
  * 
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -33,38 +33,167 @@
 #include "pdump_km.h"
 
 
-static IMG_VOID SGXResetSoftReset(PVRSRV_SGXDEV_INFO	*psDevInfo,
-								  IMG_BOOL				bResetBIF,
-								  IMG_UINT32			ui32PDUMPFlags,
-								  IMG_BOOL				bPDump)
+IMG_VOID SGXInitClocks(PVRSRV_SGXDEV_INFO	*psDevInfo,
+					   IMG_UINT32			ui32PDUMPFlags)
 {
-	IMG_UINT32 ui32SoftResetRegVal;
+	IMG_UINT32	ui32RegVal;
+	
+#if !defined(PDUMP)
+	PVR_UNREFERENCED_PARAMETER(ui32PDUMPFlags);
+#endif 
+	
+	ui32RegVal = psDevInfo->ui32ClkGateCtl;
+	OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_CLKGATECTL, ui32RegVal);
+	PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_CLKGATECTL, ui32RegVal, ui32PDUMPFlags);
+
+#if defined(EUR_CR_CLKGATECTL2)
+	ui32RegVal = psDevInfo->ui32ClkGateCtl2;
+	OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_CLKGATECTL2, ui32RegVal);
+	PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_CLKGATECTL2, ui32RegVal, ui32PDUMPFlags);
+#endif
+}
 
-#if defined(SGX_FEATURE_MP)
-	ui32SoftResetRegVal =
-					EUR_CR_MASTER_SOFT_RESET_IPF_RESET_MASK  |
-					EUR_CR_MASTER_SOFT_RESET_DPM_RESET_MASK  |
-					EUR_CR_MASTER_SOFT_RESET_VDM_RESET_MASK;
 
-#if defined(SGX_FEATURE_PTLA)
-	ui32SoftResetRegVal |= EUR_CR_MASTER_SOFT_RESET_PTLA_RESET_MASK;
-#endif
-#if defined(SGX_FEATURE_SYSTEM_CACHE)
-	ui32SoftResetRegVal |= EUR_CR_MASTER_SOFT_RESET_SLC_RESET_MASK;
-#endif
+static IMG_VOID SGXResetInitBIFContexts(PVRSRV_SGXDEV_INFO	*psDevInfo,
+										IMG_UINT32			ui32PDUMPFlags)
+{
+	IMG_UINT32	ui32RegVal;
 
-	if (bResetBIF)
+#if !defined(PDUMP)
+	PVR_UNREFERENCED_PARAMETER(ui32PDUMPFlags);
+#endif 
+
+	ui32RegVal = 0;
+	OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32RegVal);
+	PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
+
+#if defined(SGX_FEATURE_MULTIPLE_MEM_CONTEXTS)
+	PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Initialise the BIF bank settings\r\n");
+	OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_BANK_SET, ui32RegVal);
+	PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_BANK_SET, ui32RegVal, ui32PDUMPFlags);
+	OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_BANK0, ui32RegVal);
+	PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_BANK0, ui32RegVal, ui32PDUMPFlags);
+#endif 
+
+	PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Initialise the BIF directory list\r\n");
+	OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_DIR_LIST_BASE0, ui32RegVal);
+	PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_DIR_LIST_BASE0, ui32RegVal, ui32PDUMPFlags);
+
+#if defined(SGX_FEATURE_MULTIPLE_MEM_CONTEXTS)
 	{
-		ui32SoftResetRegVal |= EUR_CR_MASTER_SOFT_RESET_BIF_RESET_MASK;
+		IMG_UINT32	ui32DirList, ui32DirListReg;
+
+		for (ui32DirList = 1;
+			 ui32DirList < SGX_FEATURE_BIF_NUM_DIRLISTS;
+			 ui32DirList++)
+		{
+			ui32DirListReg = EUR_CR_BIF_DIR_LIST_BASE1 + 4 * (ui32DirList - 1);
+			OSWriteHWReg(psDevInfo->pvRegsBaseKM, ui32DirListReg, ui32RegVal);
+			PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, ui32DirListReg, ui32RegVal, ui32PDUMPFlags);
+		}
 	}
+#endif 
+}
+
+
+static IMG_VOID SGXResetSetupBIFContexts(PVRSRV_SGXDEV_INFO	*psDevInfo,
+										 IMG_UINT32			ui32PDUMPFlags)
+{
+	IMG_UINT32	ui32RegVal;
+
+#if !defined(PDUMP)
+	PVR_UNREFERENCED_PARAMETER(ui32PDUMPFlags);
+#endif 
+	
+	#if defined(SGX_FEATURE_MULTIPLE_MEM_CONTEXTS)
+	
+	ui32RegVal = (SGX_BIF_DIR_LIST_INDEX_EDM << EUR_CR_BIF_BANK0_INDEX_EDM_SHIFT);
+
+	#if defined(SGX_FEATURE_2D_HARDWARE) && !defined(SGX_FEATURE_PTLA)
+	
+	ui32RegVal |= (SGX_BIF_DIR_LIST_INDEX_EDM << EUR_CR_BIF_BANK0_INDEX_2D_SHIFT);
+	#endif 
+
+	#if defined(FIX_HW_BRN_23410)
+	
+	ui32RegVal |= (SGX_BIF_DIR_LIST_INDEX_EDM << EUR_CR_BIF_BANK0_INDEX_TA_SHIFT);
+	#endif 
+
+	OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_BANK0, ui32RegVal);
+	PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Set up EDM requestor page table in BIF\r\n");
+	PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_BANK0, ui32RegVal, ui32PDUMPFlags);
+	#endif 
 
-	OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_SOFT_RESET, ui32SoftResetRegVal);
-	if (bPDump)
 	{
-		PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_MASTER_SOFT_RESET, ui32SoftResetRegVal, ui32PDUMPFlags);
+		IMG_UINT32	ui32EDMDirListReg;
+
+		
+		#if (SGX_BIF_DIR_LIST_INDEX_EDM == 0)
+		ui32EDMDirListReg = EUR_CR_BIF_DIR_LIST_BASE0;
+		#else
+		
+		ui32EDMDirListReg = EUR_CR_BIF_DIR_LIST_BASE1 + 4 * (SGX_BIF_DIR_LIST_INDEX_EDM - 1);
+		#endif 
+
+		ui32RegVal = psDevInfo->sKernelPDDevPAddr.uiAddr >> SGX_MMU_PDE_ADDR_ALIGNSHIFT;
+		
+#if defined(FIX_HW_BRN_28011)
+		OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_DIR_LIST_BASE0, ui32RegVal);
+		PDUMPPDREGWITHFLAGS(&psDevInfo->sMMUAttrib, EUR_CR_BIF_DIR_LIST_BASE0, ui32RegVal, ui32PDUMPFlags, PDUMP_PD_UNIQUETAG);
+#endif
+
+		OSWriteHWReg(psDevInfo->pvRegsBaseKM, ui32EDMDirListReg, ui32RegVal);
+		PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Initialise the EDM's directory list base\r\n");
+		PDUMPPDREGWITHFLAGS(&psDevInfo->sMMUAttrib, ui32EDMDirListReg, ui32RegVal, ui32PDUMPFlags, PDUMP_PD_UNIQUETAG);
 	}
+}
+
+
+static IMG_VOID SGXResetSleep(PVRSRV_SGXDEV_INFO	*psDevInfo,
+							  IMG_UINT32			ui32PDUMPFlags,
+							  IMG_BOOL				bPDump)
+{
+#if defined(PDUMP) || defined(EMULATOR)
+	IMG_UINT32	ui32ReadRegister;
+
+	#if defined(SGX_FEATURE_MP)
+	ui32ReadRegister = EUR_CR_MASTER_SOFT_RESET;
+	#else
+	ui32ReadRegister = EUR_CR_SOFT_RESET;
+	#endif 
+#endif
+
+#if !defined(PDUMP)
+	PVR_UNREFERENCED_PARAMETER(ui32PDUMPFlags);
 #endif 
 
+	
+	OSWaitus(100 * 1000000 / psDevInfo->ui32CoreClockSpeed);
+	if (bPDump)
+	{
+		PDUMPIDLWITHFLAGS(30, ui32PDUMPFlags);
+#if defined(PDUMP)
+		PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Read back to flush the register writes\r\n");
+		PDumpRegRead(SGX_PDUMPREG_NAME, ui32ReadRegister, ui32PDUMPFlags);
+#endif
+	}
+
+#if defined(EMULATOR)
+	
+
+	OSReadHWReg(psDevInfo->pvRegsBaseKM, ui32ReadRegister);
+#endif
+}
+
+
+#if !defined(SGX_FEATURE_MP)
+static IMG_VOID SGXResetSoftReset(PVRSRV_SGXDEV_INFO	*psDevInfo,
+								  IMG_BOOL				bResetBIF,
+								  IMG_UINT32			ui32PDUMPFlags,
+								  IMG_BOOL				bPDump)
+{
+	IMG_UINT32 ui32SoftResetRegVal;
+
 	ui32SoftResetRegVal =
 					
 					EUR_CR_SOFT_RESET_DPM_RESET_MASK |
@@ -139,27 +268,6 @@ static IMG_VOID SGXResetSoftReset(PVRSRV_SGXDEV_INFO	*psDevInfo,
 }
 
 
-static IMG_VOID SGXResetSleep(PVRSRV_SGXDEV_INFO	*psDevInfo,
-							  IMG_UINT32			ui32PDUMPFlags,
-							  IMG_BOOL				bPDump)
-{
-#if !defined(PDUMP)
-	PVR_UNREFERENCED_PARAMETER(ui32PDUMPFlags);
-#endif 
-
-	
-	OSWaitus(100 * 1000000 / psDevInfo->ui32CoreClockSpeed);
-	if (bPDump)
-	{
-		PDUMPIDLWITHFLAGS(30, ui32PDUMPFlags);
-#if defined(PDUMP)
-		PDumpRegRead(SGX_PDUMPREG_NAME, EUR_CR_SOFT_RESET, ui32PDUMPFlags);
-#endif
-	}
-
-}
-
-
 static IMG_VOID SGXResetInvalDC(PVRSRV_SGXDEV_INFO	*psDevInfo,
 							    IMG_UINT32			ui32PDUMPFlags,
 								IMG_BOOL			bPDump)
@@ -199,8 +307,9 @@ static IMG_VOID SGXResetInvalDC(PVRSRV_SGXDEV_INFO	*psDevInfo,
 		if (PollForValueKM((IMG_UINT32 *)((IMG_UINT8*)psDevInfo->pvRegsBaseKM + EUR_CR_BIF_MEM_REQ_STAT),
 							0,
 							EUR_CR_BIF_MEM_REQ_STAT_READS_MASK,
+							MAX_HW_TIME_US,
 							MAX_HW_TIME_US/WAIT_TRY_COUNT,
-							WAIT_TRY_COUNT) != PVRSRV_OK)
+							IMG_FALSE) != PVRSRV_OK)
 		{
 			PVR_DPF((PVR_DBG_ERROR,"Wait for DC invalidate failed."));
 			PVR_DBG_BREAK;
@@ -208,16 +317,18 @@ static IMG_VOID SGXResetInvalDC(PVRSRV_SGXDEV_INFO	*psDevInfo,
 
 		if (bPDump)
 		{
-			PDUMPREGPOLWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_MEM_REQ_STAT, 0, EUR_CR_BIF_MEM_REQ_STAT_READS_MASK, ui32PDUMPFlags);
+			PDUMPREGPOLWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_MEM_REQ_STAT, 0, EUR_CR_BIF_MEM_REQ_STAT_READS_MASK, ui32PDUMPFlags, PDUMP_POLL_OPERATOR_EQUAL);
 		}
 	}
 #endif 
 }
+#endif 
 
 
 IMG_VOID SGXReset(PVRSRV_SGXDEV_INFO	*psDevInfo,
 				  IMG_BOOL				bHardwareRecovery,
 				  IMG_UINT32			ui32PDUMPFlags)
+#if !defined(SGX_FEATURE_MP)
 {
 	IMG_UINT32 ui32RegVal;
 #if defined(EUR_CR_BIF_INT_STAT_FAULT_REQ_MASK)
@@ -226,12 +337,10 @@ IMG_VOID SGXReset(PVRSRV_SGXDEV_INFO	*psDevInfo,
 	const IMG_UINT32 ui32BifFaultMask = EUR_CR_BIF_INT_STAT_FAULT_MASK;
 #endif
 
-#ifndef PDUMP
+#if !defined(PDUMP)
 	PVR_UNREFERENCED_PARAMETER(ui32PDUMPFlags);
 #endif 
 
-	psDevInfo->ui32NumResets++;
-
 	PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Start of SGX reset sequence\r\n");
 
 #if defined(FIX_HW_BRN_23944)
@@ -273,37 +382,7 @@ IMG_VOID SGXReset(PVRSRV_SGXDEV_INFO	*psDevInfo,
 	PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_36BIT_ADDRESSING, EUR_CR_BIF_36BIT_ADDRESSING_ENABLE_MASK, ui32PDUMPFlags);
 #endif
 
-	ui32RegVal = 0;
-	OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32RegVal);
-	PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
-#if defined(SGX_FEATURE_MP)
-	OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_BIF_CTRL, ui32RegVal);
-	PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_MASTER_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
-#endif 
-#if defined(SGX_FEATURE_MULTIPLE_MEM_CONTEXTS)
-	OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_BANK_SET, ui32RegVal);
-	PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_BANK_SET, ui32RegVal, ui32PDUMPFlags);
-	OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_BANK0, ui32RegVal);
-	PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_BANK0, ui32RegVal, ui32PDUMPFlags);
-#endif 
-
-	OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_DIR_LIST_BASE0, ui32RegVal);
-	PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_DIR_LIST_BASE0, ui32RegVal, ui32PDUMPFlags);
-
-#if defined(SGX_FEATURE_MULTIPLE_MEM_CONTEXTS)
-	{
-		IMG_UINT32	ui32DirList, ui32DirListReg;
-
-		for (ui32DirList = 1;
-			 ui32DirList < SGX_FEATURE_BIF_NUM_DIRLISTS;
-			 ui32DirList++)
-		{
-			ui32DirListReg = EUR_CR_BIF_DIR_LIST_BASE1 + 4 * (ui32DirList - 1);
-			OSWriteHWReg(psDevInfo->pvRegsBaseKM, ui32DirListReg, ui32RegVal);
-			PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, ui32DirListReg, ui32RegVal, ui32PDUMPFlags);
-		}
-	}
-#endif 
+	SGXResetInitBIFContexts(psDevInfo, ui32PDUMPFlags);
 
 #if defined(EUR_CR_BIF_MEM_ARB_CONFIG)
 	
@@ -316,30 +395,6 @@ IMG_VOID SGXReset(PVRSRV_SGXDEV_INFO	*psDevInfo,
 #endif 
 
 #if defined(SGX_FEATURE_SYSTEM_CACHE)
-#if defined(SGX_FEATURE_MP)
-	#if defined(SGX_BYPASS_SYSTEM_CACHE)
-		#error SGX_BYPASS_SYSTEM_CACHE not supported
-	#else
-		ui32RegVal = EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_REQ0_MASK |
-		#if defined(FIX_HW_BRN_30954)
-						EUR_CR_MASTER_SLC_CTRL_DISABLE_REORDERING_MASK |
-		#endif
-						(0xC << EUR_CR_MASTER_SLC_CTRL_ARB_PAGE_SIZE_SHIFT);
-		OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_SLC_CTRL, ui32RegVal);
-		PDUMPREG(SGX_PDUMPREG_NAME, EUR_CR_MASTER_SLC_CTRL, ui32RegVal);
-
-		ui32RegVal = EUR_CR_MASTER_SLC_CTRL_BYPASS_BYP_CC_MASK;
-	#if defined(FIX_HW_BRN_31195)
-		ui32RegVal |= EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE0_MASK |
-				EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE1_MASK |
-				EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE2_MASK |
-				EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE3_MASK |
-				EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_TA_MASK;
-	#endif
-		OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_SLC_CTRL_BYPASS, ui32RegVal);
-		PDUMPREG(SGX_PDUMPREG_NAME, EUR_CR_MASTER_SLC_CTRL_BYPASS, ui32RegVal);
-	#endif 
-#else
 	#if defined(SGX_BYPASS_SYSTEM_CACHE)
 		
 		ui32RegVal = MNE_CR_CTRL_BYPASS_ALL_MASK;
@@ -350,11 +405,14 @@ IMG_VOID SGXReset(PVRSRV_SGXDEV_INFO	*psDevInfo,
 			
 			ui32RegVal = MNE_CR_CTRL_BYP_CC_MASK;
 		#endif
+		#if defined(FIX_HW_BRN_34028)
+			
+			ui32RegVal |= (8 << MNE_CR_CTRL_BYPASS_SHIFT);
+		#endif
 	#endif 
 	OSWriteHWReg(psDevInfo->pvRegsBaseKM, MNE_CR_CTRL, ui32RegVal);
 	PDUMPREG(SGX_PDUMPREG_NAME, MNE_CR_CTRL, ui32RegVal);
 #endif 
-#endif 
 
 	if (bHardwareRecovery)
 	{
@@ -438,43 +496,7 @@ IMG_VOID SGXReset(PVRSRV_SGXDEV_INFO	*psDevInfo,
 
 	
 
-	#if defined(SGX_FEATURE_MULTIPLE_MEM_CONTEXTS)
-	
-	ui32RegVal = (SGX_BIF_DIR_LIST_INDEX_EDM << EUR_CR_BIF_BANK0_INDEX_EDM_SHIFT);
-
-	#if defined(SGX_FEATURE_2D_HARDWARE) && !defined(SGX_FEATURE_PTLA)
-	
-	ui32RegVal |= (SGX_BIF_DIR_LIST_INDEX_EDM << EUR_CR_BIF_BANK0_INDEX_2D_SHIFT);
-	#endif 
-
-	#if defined(FIX_HW_BRN_23410)
-	
-	ui32RegVal |= (SGX_BIF_DIR_LIST_INDEX_EDM << EUR_CR_BIF_BANK0_INDEX_TA_SHIFT);
-	#endif 
-
-	OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_BANK0, ui32RegVal);
-	PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_BANK0, ui32RegVal, ui32PDUMPFlags);
-	#endif 
-
-	{
-		IMG_UINT32	ui32EDMDirListReg;
-
-		
-		#if (SGX_BIF_DIR_LIST_INDEX_EDM == 0)
-		ui32EDMDirListReg = EUR_CR_BIF_DIR_LIST_BASE0;
-		#else
-		
-		ui32EDMDirListReg = EUR_CR_BIF_DIR_LIST_BASE1 + 4 * (SGX_BIF_DIR_LIST_INDEX_EDM - 1);
-		#endif 
-
-#if defined(FIX_HW_BRN_28011)
-		OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_DIR_LIST_BASE0, psDevInfo->sKernelPDDevPAddr.uiAddr>>SGX_MMU_PDE_ADDR_ALIGNSHIFT);
-		PDUMPPDREGWITHFLAGS(&psDevInfo->sMMUAttrib, EUR_CR_BIF_DIR_LIST_BASE0, psDevInfo->sKernelPDDevPAddr.uiAddr>>SGX_MMU_PDE_ADDR_ALIGNSHIFT, ui32PDUMPFlags, PDUMP_PD_UNIQUETAG);
-#endif
-
-		OSWriteHWReg(psDevInfo->pvRegsBaseKM, ui32EDMDirListReg, psDevInfo->sKernelPDDevPAddr.uiAddr>>SGX_MMU_PDE_ADDR_ALIGNSHIFT);
-		PDUMPPDREGWITHFLAGS(&psDevInfo->sMMUAttrib, ui32EDMDirListReg, psDevInfo->sKernelPDDevPAddr.uiAddr>>SGX_MMU_PDE_ADDR_ALIGNSHIFT, ui32PDUMPFlags, PDUMP_PD_UNIQUETAG);
-	}
+	SGXResetSetupBIFContexts(psDevInfo, ui32PDUMPFlags);
 
 #if defined(SGX_FEATURE_2D_HARDWARE) && !defined(SGX_FEATURE_PTLA)
 	
@@ -493,10 +515,6 @@ IMG_VOID SGXReset(PVRSRV_SGXDEV_INFO	*psDevInfo,
 
 	
 	ui32RegVal = 0;
-#if defined(SGX_FEATURE_MP)
-	OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_SOFT_RESET, ui32RegVal);
-	PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_MASTER_SOFT_RESET, ui32RegVal, ui32PDUMPFlags);
-#endif 
 	OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_SOFT_RESET, ui32RegVal);
 	PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_SOFT_RESET, ui32RegVal, ui32PDUMPFlags);
 
@@ -506,4 +524,146 @@ IMG_VOID SGXReset(PVRSRV_SGXDEV_INFO	*psDevInfo,
 	PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "End of SGX reset sequence\r\n");
 }
 
+#else
+
+{
+	IMG_UINT32 ui32RegVal;
+	
+	PVR_UNREFERENCED_PARAMETER(bHardwareRecovery);
+
+#if !defined(PDUMP)
+	PVR_UNREFERENCED_PARAMETER(ui32PDUMPFlags);
+#endif 
+
+	PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Start of SGX MP reset sequence\r\n");
+
+	
+	ui32RegVal = EUR_CR_MASTER_SOFT_RESET_BIF_RESET_MASK  |
+				 EUR_CR_MASTER_SOFT_RESET_IPF_RESET_MASK  |
+				 EUR_CR_MASTER_SOFT_RESET_DPM_RESET_MASK  |
+				 EUR_CR_MASTER_SOFT_RESET_VDM_RESET_MASK;
+
+#if defined(SGX_FEATURE_PTLA)
+	ui32RegVal |= EUR_CR_MASTER_SOFT_RESET_PTLA_RESET_MASK;
+#endif
+#if defined(SGX_FEATURE_SYSTEM_CACHE)
+	ui32RegVal |= EUR_CR_MASTER_SOFT_RESET_SLC_RESET_MASK;
+#endif
+
+	
+	ui32RegVal |= EUR_CR_MASTER_SOFT_RESET_CORE_RESET_MASK(0)  |
+				  EUR_CR_MASTER_SOFT_RESET_CORE_RESET_MASK(1)  |
+				  EUR_CR_MASTER_SOFT_RESET_CORE_RESET_MASK(2)  |
+				  EUR_CR_MASTER_SOFT_RESET_CORE_RESET_MASK(3);
+
+	OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_SOFT_RESET, ui32RegVal);
+	PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Soft reset hydra partition, hard reset the cores\r\n");
+	PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_MASTER_SOFT_RESET, ui32RegVal, ui32PDUMPFlags);
+
+	SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
+
+	ui32RegVal = 0;
+	OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_BIF_CTRL, ui32RegVal);
+	PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Initialise the hydra BIF control\r\n");
+	PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_MASTER_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
+
+#if defined(SGX_FEATURE_SYSTEM_CACHE)
+	#if defined(SGX_BYPASS_SYSTEM_CACHE)
+		#error SGX_BYPASS_SYSTEM_CACHE not supported
+	#else
+		ui32RegVal = EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_REQ0_MASK |
+		#if defined(FIX_HW_BRN_30954)
+						EUR_CR_MASTER_SLC_CTRL_DISABLE_REORDERING_MASK |
+		#endif
+		#if defined(PVR_SLC_8KB_ADDRESS_MODE)
+						(4 << EUR_CR_MASTER_SLC_CTRL_ADDR_DECODE_MODE_SHIFT) |
+		#endif
+		#if defined(FIX_HW_BRN_33809)
+			(2 << EUR_CR_MASTER_SLC_CTRL_ADDR_DECODE_MODE_SHIFT) |
+		#endif
+						(0xC << EUR_CR_MASTER_SLC_CTRL_ARB_PAGE_SIZE_SHIFT);
+		OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_SLC_CTRL, ui32RegVal);
+		PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Initialise the hydra SLC control\r\n");
+		PDUMPREG(SGX_PDUMPREG_NAME, EUR_CR_MASTER_SLC_CTRL, ui32RegVal);
+
+		ui32RegVal = EUR_CR_MASTER_SLC_CTRL_BYPASS_BYP_CC_MASK;
+	#if defined(FIX_HW_BRN_31620)
+		ui32RegVal |= EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_MMU_MASK;
+	#endif
+	#if defined(FIX_HW_BRN_31195)
+		ui32RegVal |= EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE0_MASK |
+				EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE1_MASK |
+				EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE2_MASK |
+				EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE3_MASK |
+				EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_TA_MASK;
+	#endif
+		OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_SLC_CTRL_BYPASS, ui32RegVal);
+		PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Initialise the hydra SLC bypass control\r\n");
+		PDUMPREG(SGX_PDUMPREG_NAME, EUR_CR_MASTER_SLC_CTRL_BYPASS, ui32RegVal);
+	#endif 
+#endif 
+
+	SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
+
+	
+	ui32RegVal = 0;
+	OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_SOFT_RESET, ui32RegVal);
+	PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Remove the resets from all of SGX\r\n");
+	PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_MASTER_SOFT_RESET, ui32RegVal, ui32PDUMPFlags);
+	
+	SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
+
+	PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Turn on the slave cores' clock gating\r\n");
+	SGXInitClocks(psDevInfo, ui32PDUMPFlags);
+
+	SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
+
+	PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Initialise the slave BIFs\r\n");
+
+#if defined(FIX_HW_BRN_31278) || defined(FIX_HW_BRN_31620) || defined(FIX_HW_BRN_31671) || defined(FIX_HW_BRN_32085)
+	#if defined(FIX_HW_BRN_31278) || defined(FIX_HW_BRN_32085)
+	
+	ui32RegVal = (1<<EUR_CR_MASTER_BIF_MMU_CTRL_ADDR_HASH_MODE_SHIFT);
+	#else
+	ui32RegVal = (1<<EUR_CR_MASTER_BIF_MMU_CTRL_ADDR_HASH_MODE_SHIFT) | EUR_CR_MASTER_BIF_MMU_CTRL_PREFETCHING_ON_MASK; 
+	#endif
+	#if !defined(FIX_HW_BRN_31620) && !defined(FIX_HW_BRN_31671)
+	
+	ui32RegVal |= EUR_CR_MASTER_BIF_MMU_CTRL_ENABLE_DC_TLB_MASK;
+	#endif
+
+	
+	OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_BIF_MMU_CTRL, ui32RegVal);
+	PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_MASTER_BIF_MMU_CTRL, ui32RegVal, ui32PDUMPFlags);
+
+	#if defined(FIX_HW_BRN_31278) || defined(FIX_HW_BRN_32085)
+	
+	ui32RegVal = (1<<EUR_CR_BIF_MMU_CTRL_ADDR_HASH_MODE_SHIFT);
+	#else
+	ui32RegVal = (1<<EUR_CR_BIF_MMU_CTRL_ADDR_HASH_MODE_SHIFT) | EUR_CR_BIF_MMU_CTRL_PREFETCHING_ON_MASK; 
+	#endif
+	#if !defined(FIX_HW_BRN_31620) && !defined(FIX_HW_BRN_31671)
+	
+	ui32RegVal |= EUR_CR_BIF_MMU_CTRL_ENABLE_DC_TLB_MASK;
+	#endif
+
+	
+	{
+		IMG_UINT32 ui32Core;
+
+		for (ui32Core=0;ui32Core<SGX_FEATURE_MP_CORE_COUNT;ui32Core++)
+		{
+			OSWriteHWReg(psDevInfo->pvRegsBaseKM, SGX_MP_CORE_SELECT(EUR_CR_BIF_MMU_CTRL, ui32Core), ui32RegVal);
+			PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, SGX_MP_CORE_SELECT(EUR_CR_BIF_MMU_CTRL, ui32Core), ui32RegVal, ui32PDUMPFlags);
+		}
+	}
+#endif
+
+	SGXResetInitBIFContexts(psDevInfo, ui32PDUMPFlags);
+	SGXResetSetupBIFContexts(psDevInfo, ui32PDUMPFlags);
+	
+	PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "End of SGX MP reset sequence\r\n");
+}	
+#endif 
+