gpu: pvr: Update to DDK 1.8@550175

 - Remove ProcessFlipV2 as Samsung SLSI implemented their own HWC
   that does not integrate with the GPU driver. This code has
   never been used in production.

 - Merge in DC interface cleanups from Prime. Does not affect
   Crespo because ProcessFlipV2 has been removed.

 - SGXDumpDebugInfo() changes to help progress various bug
   investigations.

Change-Id: I0d48253bfb7c17fea0795b63e48b2e026111dd2c

9 files changed, 55 insertions, 124 deletions

diff --git a/drivers/gpu/pvr/deviceclass.c b/drivers/gpu/pvr/deviceclass.c
index d011bac..f8c83f6 100644
--- a/drivers/gpu/pvr/deviceclass.c
+++ b/drivers/gpu/pvr/deviceclass.c
@@ -1700,7 +1700,7 @@ PVRSRV_ERROR PVRSRVSwapToDCBuffer2KM(IMG_HANDLE	hDeviceKM,
 	psFlipCmd->pvPrivData = pvPrivData;
 	psFlipCmd->ui32PrivDataLength = ui32PrivDataLength;
 
-	psFlipCmd->ppvMemInfos = ppvMemInfos;
+	psFlipCmd->ppsMemInfos = (PDC_MEM_INFO *)ppvMemInfos;
 	psFlipCmd->ui32NumMemInfos = ui32NumMemSyncInfos;
 
 	SysAcquireData(&psSysData);
@@ -1988,6 +1988,29 @@ IMG_VOID IMG_CALLCONV PVRSRVSetDCState(IMG_UINT32 ui32State)
 										ui32State);
 }
 
+static PVRSRV_ERROR
+PVRSRVDCMemInfoGetCpuVAddr(PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo,
+						   IMG_CPU_VIRTADDR *pVAddr)
+{
+	*pVAddr = psKernelMemInfo->pvLinAddrKM;
+	return PVRSRV_OK;
+}
+
+static PVRSRV_ERROR
+PVRSRVDCMemInfoGetCpuPAddr(PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo,
+						   IMG_SIZE_T uByteOffset, IMG_CPU_PHYADDR *pPAddr)
+{
+	*pPAddr = OSMemHandleToCpuPAddr(psKernelMemInfo->sMemBlk.hOSMemHandle, uByteOffset);
+	return PVRSRV_OK;
+}
+
+static PVRSRV_ERROR
+PVRSRVDCMemInfoGetByteSize(PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo,
+						   IMG_SIZE_T *uByteSize)
+{
+	*uByteSize = psKernelMemInfo->uAllocSize;
+	return PVRSRV_OK;
+}
 
 IMG_EXPORT
 IMG_BOOL PVRGetDisplayClassJTable(PVRSRV_DC_DISP2SRV_KMJTABLE *psJTable)
@@ -2008,7 +2031,9 @@ IMG_BOOL PVRGetDisplayClassJTable(PVRSRV_DC_DISP2SRV_KMJTABLE *psJTable)
 #if defined(SUPPORT_CUSTOM_SWAP_OPERATIONS)
 	psJTable->pfnPVRSRVFreeCmdCompletePacket = &PVRSRVFreeCommandCompletePacketKM;
 #endif
-
+	psJTable->pfnPVRSRVDCMemInfoGetCpuVAddr = &PVRSRVDCMemInfoGetCpuVAddr;
+	psJTable->pfnPVRSRVDCMemInfoGetCpuPAddr = &PVRSRVDCMemInfoGetCpuPAddr;
+	psJTable->pfnPVRSRVDCMemInfoGetByteSize = &PVRSRVDCMemInfoGetByteSize;
 	return IMG_TRUE;
 }
 
diff --git a/drivers/gpu/pvr/kerneldisplay.h b/drivers/gpu/pvr/kerneldisplay.h
index 76ee4b8..7e9ba51 100644
--- a/drivers/gpu/pvr/kerneldisplay.h
+++ b/drivers/gpu/pvr/kerneldisplay.h
@@ -106,6 +106,12 @@ typedef PVRSRV_ERROR (*PFN_DC_REGISTER_POWER)(IMG_UINT32, PFN_PRE_POWER, PFN_POS
 											  PFN_PRE_CLOCKSPEED_CHANGE, PFN_POST_CLOCKSPEED_CHANGE,
 											  IMG_HANDLE, PVRSRV_DEV_POWER_STATE, PVRSRV_DEV_POWER_STATE);
 
+typedef struct _PVRSRV_KERNEL_MEM_INFO_* PDC_MEM_INFO;
+
+typedef PVRSRV_ERROR (*PFN_DC_MEMINFO_GET_CPU_VADDR)(PDC_MEM_INFO, IMG_CPU_VIRTADDR *pVAddr);
+typedef PVRSRV_ERROR (*PFN_DC_MEMINFO_GET_CPU_PADDR)(PDC_MEM_INFO, IMG_SIZE_T uByteOffset, IMG_CPU_PHYADDR *pPAddr);
+typedef PVRSRV_ERROR (*PFN_DC_MEMINFO_GET_BYTE_SIZE)(PDC_MEM_INFO, IMG_SIZE_T *uByteSize);
+
 typedef struct PVRSRV_DC_DISP2SRV_KMJTABLE_TAG
 {
 	IMG_UINT32						ui32TableSize;
@@ -118,6 +124,10 @@ typedef struct PVRSRV_DC_DISP2SRV_KMJTABLE_TAG
 	PFN_DC_REGISTER_SYS_ISR			pfnPVRSRVRegisterSystemISRHandler;
 	PFN_DC_REGISTER_POWER			pfnPVRSRVRegisterPowerDevice;
 	PFN_DC_CMD_COMPLETE				pfnPVRSRVFreeCmdCompletePacket;
+	PFN_DC_MEMINFO_GET_CPU_VADDR	pfnPVRSRVDCMemInfoGetCpuVAddr;
+	PFN_DC_MEMINFO_GET_CPU_PADDR	pfnPVRSRVDCMemInfoGetCpuPAddr;
+	PFN_DC_MEMINFO_GET_BYTE_SIZE	pfnPVRSRVDCMemInfoGetByteSize;
+
 } PVRSRV_DC_DISP2SRV_KMJTABLE, *PPVRSRV_DC_DISP2SRV_KMJTABLE;
 
 
@@ -168,7 +178,7 @@ typedef struct DISPLAYCLASS_FLIP_COMMAND2_TAG
 	IMG_UINT32 ui32PrivDataLength;
 
 	
-	IMG_VOID **ppvMemInfos;
+	PDC_MEM_INFO *ppsMemInfos;
 
 	
 	IMG_UINT32 ui32NumMemInfos;
diff --git a/drivers/gpu/pvr/module.c b/drivers/gpu/pvr/module.c
index ff5eed5..cc9334b 100644
--- a/drivers/gpu/pvr/module.c
+++ b/drivers/gpu/pvr/module.c
@@ -128,6 +128,7 @@ MODULE_PARM_DESC(gPVRDebugLevel, "Sets the level of debug output (default 0x7)")
 #include <linux/omap_ion.h>
 extern struct ion_device *omap_ion_device;
 struct ion_client *gpsIONClient;
+EXPORT_SYMBOL(gpsIONClient);
 #endif 
 
  
diff --git a/drivers/gpu/pvr/pvrversion.h b/drivers/gpu/pvr/pvrversion.h
index 8f987ef..c887f58 100644
--- a/drivers/gpu/pvr/pvrversion.h
+++ b/drivers/gpu/pvr/pvrversion.h
@@ -36,7 +36,7 @@
 
 #define PVRVERSION_FAMILY           "sgxddk"
 #define PVRVERSION_BRANCHNAME       "1.8"
-#define PVRVERSION_BUILD             300406
+#define PVRVERSION_BUILD             550175
 #define PVRVERSION_BSCONTROL        "CustomerGoogle_Android_ogles1_ogles2_GPL"
 
 #define PVRVERSION_STRING           "CustomerGoogle_Android_ogles1_ogles2_GPL sgxddk 18 1.8@" PVR_STR2(PVRVERSION_BUILD)
@@ -44,8 +44,8 @@
 
 #define COPYRIGHT_TXT               "Copyright (c) Imagination Technologies Ltd. All Rights Reserved."
 
-#define PVRVERSION_BUILD_HI          30
-#define PVRVERSION_BUILD_LO          406
+#define PVRVERSION_BUILD_HI          55
+#define PVRVERSION_BUILD_LO          175
 #define PVRVERSION_STRING_NUMERIC    PVR_STR2(PVRVERSION_MAJ) "." PVR_STR2(PVRVERSION_MIN) "." PVR_STR2(PVRVERSION_BUILD_HI) "." PVR_STR2(PVRVERSION_BUILD_LO)
 
 #endif /* _PVRVERSION_H_ */
diff --git a/drivers/gpu/pvr/s3c_lcd/s3c_displayclass.c b/drivers/gpu/pvr/s3c_lcd/s3c_displayclass.c
index 47c53ac..ff65c20 100644
--- a/drivers/gpu/pvr/s3c_lcd/s3c_displayclass.c
+++ b/drivers/gpu/pvr/s3c_lcd/s3c_displayclass.c
@@ -815,98 +815,6 @@ static IMG_BOOL ProcessFlipV1(IMG_HANDLE hCmdCookie,
 	return IMG_TRUE;
 }
 
-/* FIXME: Shouldn't be using internal interfaces like this */ 
-#include "servicesint.h"
-#include "services.h"
-#include "mm.h"
-
-/************* MUST STAY IN SYNC WITH USER *************/
-
-typedef struct s5pc110_hwc_rect
-{
-	s32 left;
-	s32 top;
-	s32 right;
-	s32 bottom;
-}
-s5pc110_hwc_rect_t;
-
-typedef struct s5pc110_hwc_layer
-{
-	s5pc110_hwc_rect_t sourceCrop;
-	s5pc110_hwc_rect_t displayFrame;
-	u32 transform;
-	u32 skip;
-}
-s5pc110_hwc_layer_t;
-
-/*******************************************************/
-
-/* Triggered by PVRSRVSwapToDCBuffer2 */ 
-static IMG_BOOL ProcessFlipV2(IMG_HANDLE hCmdCookie,
-							  S3C_LCD_DEVINFO *psDevInfo,
-							  IMG_UINT32 ui32SwapInterval,
-							  IMG_VOID **ppvMemInfos,
-							  IMG_UINT32 ui32NumMemInfos,
-							  s5pc110_hwc_layer_t *psHwcData)
-{
-	PVRSRV_KERNEL_MEM_INFO **ppsMemInfos =
-		(PVRSRV_KERNEL_MEM_INFO **)ppvMemInfos;
-	S3C_FRAME_BUFFER *psFb = NULL;
-	LinuxMemArea *psDestArea;
-	IMG_UINT32 i;
-
-	BUG_ON(psHwcData[0].skip != 1);
-	psDestArea = ppsMemInfos[0]->sMemBlk.hOSMemHandle;
-
-	/* Reverse-lookup of referenced back buffer */
-
-	/* Check the system buffer */
-	psFb = &psDevInfo->sSysBuffer;
-	if(psFb->bufferPAddr.uiAddr != LinuxMemAreaToCpuPAddr(psDestArea, 0).uiAddr)
-	{
-		/* Check the back buffers */
-		for(i = 0; i < psDevInfo->ui32NumFrameBuffers; i++)
-		{
-			psFb = &psDevInfo->asBackBuffers[i];
-			if(psFb->bufferPAddr.uiAddr == LinuxMemAreaToCpuPAddr(psDestArea, 0).uiAddr)
-				break;
-		}
-
-		if(i == psDevInfo->ui32NumFrameBuffers)
-		{
-			printk("FB reverse-lookup failed for 0x%.8x\n",
-				   LinuxMemAreaToCpuPAddr(psDestArea, 0).uiAddr);
-			gsPVRJTable.pfnPVRSRVCmdComplete(hCmdCookie, IMG_FALSE);
-			return IMG_FALSE;
-		}
-	}
-
-	/* Now perform FIMC blits */
-	for(i = 1; i < ui32NumMemInfos; i++)
-	{
-		LinuxMemArea *psSourceArea = ppsMemInfos[i]->sMemBlk.hOSMemHandle;
-
-		BUG_ON(psHwcData[i].skip == 1);
-
-		/* SLSI need to implement this! */
-		printk("FIMC blit: 0x%.8x -> 0x%.8x {%d,%d,%d,%d}->{%d,%d,%d,%d}, tr %d\n",
-			   LinuxMemAreaToCpuPAddr(psSourceArea, 0).uiAddr,
-			   LinuxMemAreaToCpuPAddr(psDestArea, 0).uiAddr,
-			   psHwcData[i].sourceCrop.left,
-			   psHwcData[i].sourceCrop.top,
-			   psHwcData[i].sourceCrop.right,
-			   psHwcData[i].sourceCrop.bottom,
-			   psHwcData[i].displayFrame.left,
-			   psHwcData[i].displayFrame.top,
-			   psHwcData[i].displayFrame.right,
-			   psHwcData[i].displayFrame.bottom,
-			   psHwcData[i].transform);
-	}
-
-	return ProcessFlipV1(hCmdCookie, psDevInfo, psFb, ui32SwapInterval);
-}
-
 static IMG_BOOL ProcessFlip(IMG_HANDLE	hCmdCookie,
 							IMG_UINT32	ui32DataSize,
 							IMG_VOID	*pvData)
@@ -936,30 +844,10 @@ static IMG_BOOL ProcessFlip(IMG_HANDLE	hCmdCookie,
 		return IMG_TRUE;
 	}
 
-	if(psFlipCmd->hExtBuffer)
-	{
-		return ProcessFlipV1(hCmdCookie,
-							 psDevInfo,
-							 psFlipCmd->hExtBuffer,
-							 psFlipCmd->ui32SwapInterval);
-	}
-	else
-	{
-		DISPLAYCLASS_FLIP_COMMAND2 *psFlipCmd2;
-		psFlipCmd2 = (DISPLAYCLASS_FLIP_COMMAND2 *)pvData;
-
-		WARN_ON(psFlipCmd2->ui32PrivDataLength !=
-				sizeof(s5pc110_hwc_layer_t) * psFlipCmd2->ui32NumMemInfos);
-
-		BUG_ON(psFlipCmd2->ui32NumMemInfos == 0);
-
-		return ProcessFlipV2(hCmdCookie,
-							 psDevInfo,
-							 psFlipCmd2->ui32SwapInterval,
-							 psFlipCmd2->ppvMemInfos,
-							 psFlipCmd2->ui32NumMemInfos,
-							 psFlipCmd2->pvPrivData);
-	}
+	return ProcessFlipV1(hCmdCookie,
+						 psDevInfo,
+						 psFlipCmd->hExtBuffer,
+						 psFlipCmd->ui32SwapInterval);
 }
 
 static S3C_BOOL InitDev(struct fb_info **s3c_fb_Info)
diff --git a/drivers/gpu/pvr/sgx/sgxinfokm.h b/drivers/gpu/pvr/sgx/sgxinfokm.h
index 2f25a87..7e2b3f9 100644
--- a/drivers/gpu/pvr/sgx/sgxinfokm.h
+++ b/drivers/gpu/pvr/sgx/sgxinfokm.h
@@ -545,6 +545,9 @@ PVRSRV_ERROR SGXPostClockSpeedChange(IMG_HANDLE				hDevHandle,
 
 IMG_VOID SGXPanic(PVRSRV_SGXDEV_INFO	*psDevInfo);
 
+IMG_VOID SGXDumpDebugInfo (PVRSRV_SGXDEV_INFO	*psDevInfo,
+						   IMG_BOOL				bDumpSGXRegs);
+
 PVRSRV_ERROR SGXDevInitCompatCheck(PVRSRV_DEVICE_NODE *psDeviceNode);
 
 #if defined(SGX_DYNAMIC_TIMING_INFO)
diff --git a/drivers/gpu/pvr/sgx/sgxinit.c b/drivers/gpu/pvr/sgx/sgxinit.c
index c13dbda..636620d 100644
--- a/drivers/gpu/pvr/sgx/sgxinit.c
+++ b/drivers/gpu/pvr/sgx/sgxinit.c
@@ -519,6 +519,7 @@ PVRSRV_ERROR SGXInitialise(PVRSRV_SGXDEV_INFO	*psDevInfo,
 	{
 		PVR_DPF((PVR_DBG_ERROR, "SGXInitialise: Wait for uKernel initialisation failed"));
 		#if !defined(FIX_HW_BRN_23281)
+		SGXDumpDebugInfo(psDevInfo, IMG_FALSE);
 		PVR_DBG_BREAK;
 		#endif 
 		return PVRSRV_ERROR_RETRY;
@@ -1012,8 +1013,8 @@ static IMG_VOID SGXDumpDebugReg (PVRSRV_SGXDEV_INFO	*psDevInfo,
 	PVR_LOG(("(P%u) %s%08X", ui32CoreNum, pszName, ui32RegVal));
 }
 
-static IMG_VOID SGXDumpDebugInfo (PVRSRV_SGXDEV_INFO	*psDevInfo,
-								  IMG_BOOL				bDumpSGXRegs)
+IMG_VOID SGXDumpDebugInfo (PVRSRV_SGXDEV_INFO	*psDevInfo,
+						   IMG_BOOL				bDumpSGXRegs)
 {
 	IMG_UINT32	ui32CoreNum;
 
diff --git a/drivers/gpu/pvr/sgx/sgxpower.c b/drivers/gpu/pvr/sgx/sgxpower.c
index 3947cdd..696941f 100644
--- a/drivers/gpu/pvr/sgx/sgxpower.c
+++ b/drivers/gpu/pvr/sgx/sgxpower.c
@@ -202,6 +202,7 @@ static IMG_VOID SGXPollForClockGating (PVRSRV_SGXDEV_INFO	*psDevInfo,
 						IMG_FALSE) != PVRSRV_OK)
 	{
 		PVR_DPF((PVR_DBG_ERROR,"SGXPollForClockGating: %s failed.", pszComment));
+		SGXDumpDebugInfo(psDevInfo, IMG_FALSE);
 		PVR_DBG_BREAK;
 	}
 	#endif 
diff --git a/drivers/gpu/pvr/sgx/sgxutils.c b/drivers/gpu/pvr/sgx/sgxutils.c
index 84cf702f..f362e06 100644
--- a/drivers/gpu/pvr/sgx/sgxutils.c
+++ b/drivers/gpu/pvr/sgx/sgxutils.c
@@ -664,6 +664,7 @@ PVRSRV_ERROR SGXCleanupRequest(PVRSRV_DEVICE_NODE *psDeviceNode,
 		if (eError != PVRSRV_OK)
 		{
 				PVR_DPF((PVR_DBG_ERROR,"SGXCleanupRequest: Failed to submit clean-up command"));
+				SGXDumpDebugInfo(psDevInfo, IMG_FALSE);
 				PVR_DBG_BREAK;
 				return eError;
 		}
@@ -679,6 +680,7 @@ PVRSRV_ERROR SGXCleanupRequest(PVRSRV_DEVICE_NODE *psDeviceNode,
 		{
 			PVR_DPF((PVR_DBG_ERROR,"SGXCleanupRequest: Wait for uKernel to clean up (%u) failed", ui32CleanupType));
 			eError = PVRSRV_ERROR_TIMEOUT;
+			SGXDumpDebugInfo(psDevInfo, IMG_FALSE);
 			PVR_DBG_BREAK;
 		}
 		#endif