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author | Andy Walls <awalls@radix.net> | 2008-11-02 18:15:28 -0300 |
---|---|---|
committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2008-12-30 09:38:00 -0200 |
commit | f7823f8f437fbbd41155f2312ef17e471199b706 (patch) | |
tree | 245f1a91956f553ce387e6caa10c875b3f4316c4 /drivers/media/video/cx18/cx18-io.c | |
parent | f2e52cd17622eed39576f113b77bbd18c577e308 (diff) | |
download | kernel_samsung_crespo-f7823f8f437fbbd41155f2312ef17e471199b706.zip kernel_samsung_crespo-f7823f8f437fbbd41155f2312ef17e471199b706.tar.gz kernel_samsung_crespo-f7823f8f437fbbd41155f2312ef17e471199b706.tar.bz2 |
V4L/DVB (9513): cx18: Reduce number of mmio read retries
cx18: Reduce number of mmio read retries to improve performance. Experiments
have shown 2 things: read retries never improve the result of a suspect mmio
read from the CX23418 (the result stays all 0xff's), and that most of the
suspected read failures are actually proper reads of values that should be
all 0xff's. This change reduces the number of read retries and keeps the
count separate from write retries.
Signed-off-by: Andy Walls <awalls@radix.net>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/video/cx18/cx18-io.c')
-rw-r--r-- | drivers/media/video/cx18/cx18-io.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/drivers/media/video/cx18/cx18-io.c b/drivers/media/video/cx18/cx18-io.c index 220fae8..0ad8dea 100644 --- a/drivers/media/video/cx18/cx18-io.c +++ b/drivers/media/video/cx18/cx18-io.c @@ -31,10 +31,10 @@ void cx18_log_statistics(struct cx18 *cx) if (!(cx18_debug & CX18_DBGFLG_INFO)) return; - for (i = 0; i <= CX18_MAX_MMIO_RETRIES; i++) + for (i = 0; i <= CX18_MAX_MMIO_WR_RETRIES; i++) CX18_DEBUG_INFO("retried_write[%d] = %d\n", i, atomic_read(&cx->mmio_stats.retried_write[i])); - for (i = 0; i <= CX18_MAX_MMIO_RETRIES; i++) + for (i = 0; i <= CX18_MAX_MMIO_RD_RETRIES; i++) CX18_DEBUG_INFO("retried_read[%d] = %d\n", i, atomic_read(&cx->mmio_stats.retried_read[i])); return; @@ -43,7 +43,7 @@ void cx18_log_statistics(struct cx18 *cx) void cx18_raw_writel_retry(struct cx18 *cx, u32 val, void __iomem *addr) { int i; - for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) { + for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) { cx18_raw_writel_noretry(cx, val, addr); if (val == cx18_raw_readl_noretry(cx, addr)) break; @@ -55,7 +55,7 @@ u32 cx18_raw_readl_retry(struct cx18 *cx, const void __iomem *addr) { int i; u32 val; - for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) { + for (i = 0; i < CX18_MAX_MMIO_RD_RETRIES; i++) { val = cx18_raw_readl_noretry(cx, addr); if (val != 0xffffffff) /* PCI bus read error */ break; @@ -68,7 +68,7 @@ u16 cx18_raw_readw_retry(struct cx18 *cx, const void __iomem *addr) { int i; u16 val; - for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) { + for (i = 0; i < CX18_MAX_MMIO_RD_RETRIES; i++) { val = cx18_raw_readw_noretry(cx, addr); if (val != 0xffff) /* PCI bus read error */ break; @@ -80,7 +80,7 @@ u16 cx18_raw_readw_retry(struct cx18 *cx, const void __iomem *addr) void cx18_writel_retry(struct cx18 *cx, u32 val, void __iomem *addr) { int i; - for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) { + for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) { cx18_writel_noretry(cx, val, addr); if (val == cx18_readl_noretry(cx, addr)) break; @@ -93,7 +93,7 @@ void _cx18_writel_expect(struct cx18 *cx, u32 val, void __iomem *addr, { int i; eval &= mask; - for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) { + for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) { cx18_writel_noretry(cx, val, addr); if (eval == (cx18_readl_noretry(cx, addr) & mask)) break; @@ -104,7 +104,7 @@ void _cx18_writel_expect(struct cx18 *cx, u32 val, void __iomem *addr, void cx18_writew_retry(struct cx18 *cx, u16 val, void __iomem *addr) { int i; - for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) { + for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) { cx18_writew_noretry(cx, val, addr); if (val == cx18_readw_noretry(cx, addr)) break; @@ -115,7 +115,7 @@ void cx18_writew_retry(struct cx18 *cx, u16 val, void __iomem *addr) void cx18_writeb_retry(struct cx18 *cx, u8 val, void __iomem *addr) { int i; - for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) { + for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) { cx18_writeb_noretry(cx, val, addr); if (val == cx18_readb_noretry(cx, addr)) break; @@ -127,7 +127,7 @@ u32 cx18_readl_retry(struct cx18 *cx, const void __iomem *addr) { int i; u32 val; - for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) { + for (i = 0; i < CX18_MAX_MMIO_RD_RETRIES; i++) { val = cx18_readl_noretry(cx, addr); if (val != 0xffffffff) /* PCI bus read error */ break; @@ -140,7 +140,7 @@ u16 cx18_readw_retry(struct cx18 *cx, const void __iomem *addr) { int i; u16 val; - for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) { + for (i = 0; i < CX18_MAX_MMIO_RD_RETRIES; i++) { val = cx18_readw_noretry(cx, addr); if (val != 0xffff) /* PCI bus read error */ break; @@ -153,7 +153,7 @@ u8 cx18_readb_retry(struct cx18 *cx, const void __iomem *addr) { int i; u8 val; - for (i = 0; i < CX18_MAX_MMIO_RETRIES; i++) { + for (i = 0; i < CX18_MAX_MMIO_RD_RETRIES; i++) { val = cx18_readb_noretry(cx, addr); if (val != 0xff) /* PCI bus read error */ break; |