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author | Magnus Damm <damm@igel.co.jp> | 2009-02-24 22:58:57 +0900 |
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committer | Paul Mundt <lethal@linux-sh.org> | 2009-02-27 16:53:50 +0900 |
commit | bdaa6e8062d7f8085d8ed94ff88c99406ad53d79 (patch) | |
tree | c68310adbcea90c5c8bdb4b4b7c6517c40ecb0de /drivers/sh | |
parent | 3e91faec47e9e12b965c952d698b0bb64847af06 (diff) | |
download | kernel_samsung_crespo-bdaa6e8062d7f8085d8ed94ff88c99406ad53d79.zip kernel_samsung_crespo-bdaa6e8062d7f8085d8ed94ff88c99406ad53d79.tar.gz kernel_samsung_crespo-bdaa6e8062d7f8085d8ed94ff88c99406ad53d79.tar.bz2 |
sh: multiple vectors per irq - base
Instead of keeping the single vector -> single linux irq mapping
we extend the intc code to support merging of vectors to a single
linux irq. This helps processors such as sh7750, sh7780 and sh7785
which have more vectors than masking ability. With this patch in
place we can modify the intc tables to use one irq per maskable
irq source. Please note the following:
- If multiple vectors share the same enum then only the
first vector will be available as a linux irq.
- Drivers may need to be rewritten to get pending irq
source from the hardware block instead of irq number.
This patch together with the sh7785 specific intc tables solves
DMA controller irq issues related to buggy interrupt masking.
Reported-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'drivers/sh')
-rw-r--r-- | drivers/sh/intc.c | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/drivers/sh/intc.c b/drivers/sh/intc.c index 58d24c5..d7b8959 100644 --- a/drivers/sh/intc.c +++ b/drivers/sh/intc.c @@ -568,6 +568,10 @@ static void __init intc_register_irq(struct intc_desc *desc, if (!data[0] && data[1]) primary = 1; + if (!data[0] && !data[1]) + pr_warning("intc: missing unique irq mask for 0x%04x\n", + irq2evt(irq)); + data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1); data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1); @@ -641,6 +645,17 @@ static unsigned int __init save_reg(struct intc_desc_int *d, return 0; } +static unsigned char *intc_evt2irq_table; + +unsigned int intc_evt2irq(unsigned int vector) +{ + unsigned int irq = evt2irq(vector); + + if (intc_evt2irq_table && intc_evt2irq_table[irq]) + irq = intc_evt2irq_table[irq]; + + return irq; +} void __init register_intc_controller(struct intc_desc *desc) { @@ -705,9 +720,41 @@ void __init register_intc_controller(struct intc_desc *desc) BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */ + /* keep the first vector only if same enum is used multiple times */ + for (i = 0; i < desc->nr_vectors; i++) { + struct intc_vect *vect = desc->vectors + i; + int first_irq = evt2irq(vect->vect); + + if (!vect->enum_id) + continue; + + for (k = i + 1; k < desc->nr_vectors; k++) { + struct intc_vect *vect2 = desc->vectors + k; + + if (vect->enum_id != vect2->enum_id) + continue; + + vect2->enum_id = 0; + + if (!intc_evt2irq_table) + intc_evt2irq_table = alloc_bootmem(NR_IRQS); + + if (!intc_evt2irq_table) { + pr_warning("intc: cannot allocate evt2irq!\n"); + continue; + } + + intc_evt2irq_table[evt2irq(vect2->vect)] = first_irq; + } + } + + /* register the vectors one by one */ for (i = 0; i < desc->nr_vectors; i++) { struct intc_vect *vect = desc->vectors + i; + if (!vect->enum_id) + continue; + intc_register_irq(desc, d, vect->enum_id, evt2irq(vect->vect)); } } |