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| author | Jesse Barnes <jbarnes@virtuousgeek.org> | 2010-02-04 10:59:27 -0800 |
|---|---|---|
| committer | H. Peter Anvin <hpa@zytor.com> | 2010-02-23 23:14:47 -0800 |
| commit | a712ffbc199849364c46e9112b93b66de08e2c26 (patch) | |
| tree | af5c32acfcbd84a1069490ed6951e5d3bd7ff079 /include/linux | |
| parent | 4966e1affb45c5fc402969e10e979407b972a7df (diff) | |
| download | kernel_samsung_crespo-a712ffbc199849364c46e9112b93b66de08e2c26.zip kernel_samsung_crespo-a712ffbc199849364c46e9112b93b66de08e2c26.tar.gz kernel_samsung_crespo-a712ffbc199849364c46e9112b93b66de08e2c26.tar.bz2 | |
x86/PCI: Moorestown PCI support
The Moorestown platform only has a few devices that actually support
PCI config cycles. The rest of the devices use an in-RAM MCFG space
for the purposes of device enumeration and initialization.
There are a few uglies in the fake support, like BAR sizes that aren't
a power of two, sizing detection, and writes to the real devices, but
other than that it's pretty straightforward.
Another way to think of this is not really as PCI at all, but just a
table in RAM describing which devices are present, their capabilities
and their offsets in MMIO space. This could have been done with a
special new firmware table on this platform, but given that we do have
some real PCI devices too, simply describing things in an MCFG type
space was pretty simple.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
LKML-Reference: <43F901BD926A4E43B106BF17856F07559FB80D08@orsmsx508.amr.corp.intel.com>
Signed-off-by: Jacob Pan <jacob.jun.pan@intel.com>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'include/linux')
| -rw-r--r-- | include/linux/pci_regs.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h index 9f2ad0a..c8f3029 100644 --- a/include/linux/pci_regs.h +++ b/include/linux/pci_regs.h @@ -507,6 +507,7 @@ #define PCI_EXT_CAP_ID_VC 2 #define PCI_EXT_CAP_ID_DSN 3 #define PCI_EXT_CAP_ID_PWR 4 +#define PCI_EXT_CAP_ID_VNDR 11 #define PCI_EXT_CAP_ID_ACS 13 #define PCI_EXT_CAP_ID_ARI 14 #define PCI_EXT_CAP_ID_ATS 15 |