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| author | Thomas Gleixner <tglx@linutronix.de> | 2006-09-28 15:38:36 +0200 |
|---|---|---|
| committer | Artem Bityutskiy <dedekind@infradead.org> | 2006-11-29 17:03:52 +0200 |
| commit | 29072b96078ffde36f03d51e6b5d0cff1ba8c7df (patch) | |
| tree | 1353a27ae7e594044c521e28abf558e3796f98c9 /include | |
| parent | f6a7ecb18dabd88bd9f28e7bece564cabe8ffe82 (diff) | |
| download | kernel_samsung_crespo-29072b96078ffde36f03d51e6b5d0cff1ba8c7df.zip kernel_samsung_crespo-29072b96078ffde36f03d51e6b5d0cff1ba8c7df.tar.gz kernel_samsung_crespo-29072b96078ffde36f03d51e6b5d0cff1ba8c7df.tar.bz2 | |
[MTD] NAND: add subpage write support
Many SLC NANDs support up to 4 writes at one NAND page. Add support
of this feature.
Signed-off-by: Artem Bityutskiy <dedekind@infradead.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/mtd/mtd.h | 2 | ||||
| -rw-r--r-- | include/linux/mtd/nand.h | 9 |
2 files changed, 11 insertions, 0 deletions
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index e34bbc9..18acb6d 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -200,6 +200,8 @@ struct mtd_info { /* ECC status information */ struct mtd_ecc_stats ecc_stats; + /* Subpage shift (NAND) */ + int subpage_sft; void *priv; diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 6fc3e07..1aeedf2 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -166,6 +166,9 @@ typedef enum { * for all large page devices, as they do not support * autoincrement.*/ #define NAND_NO_READRDY 0x00000100 +/* Chip does not allow subpage writes */ +#define NAND_NO_SUBPAGE_WRITE 0x00000200 + /* Options valid for Samsung large page devices */ #define NAND_SAMSUNG_LP_OPTIONS \ @@ -193,6 +196,9 @@ typedef enum { /* Nand scan has allocated controller struct */ #define NAND_CONTROLLER_ALLOC 0x80000000 +/* Cell info constants */ +#define NAND_CI_CHIPNR_MSK 0x03 +#define NAND_CI_CELLTYPE_MSK 0x0C /* * nand_state_t - chip states @@ -341,6 +347,7 @@ struct nand_buffers { * @chipsize: [INTERN] the size of one chip for multichip arrays * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf + * @subpagesize: [INTERN] holds the subpagesize * @ecclayout: [REPLACEABLE] the default ecc placement scheme * @bbt: [INTERN] bad block table pointer * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup @@ -388,6 +395,8 @@ struct nand_chip { unsigned long chipsize; int pagemask; int pagebuf; + int subpagesize; + uint8_t cellinfo; int badblockpos; nand_state_t state; |