S5PC11X: BATTERY: definite bit-shift and bit-mask of max8998 register

Change-Id: Ic13edb28216a27cf27137b7a6be9deefe53c18a1
Signed-off-by: Minsu Kim <minsu78.kim@samsung.com>

1 files changed, 141 insertions, 0 deletions

diff --git a/include/linux/mfd/max8998-private.h b/include/linux/mfd/max8998-private.h
index effa5d3..1877d15 100644..100755
--- a/include/linux/mfd/max8998-private.h
+++ b/include/linux/mfd/max8998-private.h
@@ -132,6 +132,147 @@ enum {
 
 #define MAX8998_ENRAMP                  (1 << 4)
 
+/* IRQ1 */
+#define MAX8998_SHIFT_PWRONR	7
+#define MAX8998_SHIFT_PWRONF	6
+#define MAX8998_SHIFT_JIGR	5
+#define MAX8998_SHIFT_JIGF	4
+#define MAX8998_SHIFT_DCINR	3
+#define MAX8998_SHIFT_DCINF	2
+
+#define MAX8998_MASK_PWRONR	(0x1 << MAX8998_SHIFT_PWRONR)
+#define MAX8998_MASK_PWRONF	(0x1 << MAX8998_SHIFT_PWRONF)
+#define MAX8998_MASK_JIGR	(0x1 << MAX8998_SHIFT_JIGR)
+#define MAX8998_MASK_JIGF	(0x1 << MAX8998_SHIFT_JIGF)
+#define MAX8998_MASK_DCINR	(0x1 << MAX8998_SHIFT_DCINR)
+#define MAX8998_MASK_DCINF	(0x1 << MAX8998_SHIFT_DCINF)
+
+/* STATUS1 */
+#define MAX8998_SHIFT_ENDKEY	7
+#define MAX8998_SHIFT_JIGON	6
+#define MAX8998_SHIFT_ALARM0	5
+#define MAX8998_SHIFT_ALARM1	4
+#define MAX8998_SHIFT_SMPL	3
+#define MAX8998_SHIFT_WTSR	2
+#define MAX8998_SHIFT_LOWBAT2	1
+#define MAX8998_SHIFT_LOWBAT1	0
+
+#define MAX8998_MASK_ENDKEY	(0x1 << MAX8998_SHIFT_ENDKEY)
+#define MAX8998_MASK_JIGON	(0x1 << MAX8998_SHIFT_JIGON)
+#define MAX8998_MASK_ALARM0	(0x1 << MAX8998_SHIFT_ALARM0)
+#define MAX8998_MASK_ALARM1	(0x1 << MAX8998_SHIFT_ALARM1)
+#define MAX8998_MASK_SMPL	(0x1 << MAX8998_SHIFT_SMPL)
+#define MAX8998_MASK_WTSR	(0x1 << MAX8998_SHIFT_WTSR)
+#define MAX8998_MASK_LOWBAT2	(0x1 << MAX8998_SHIFT_LOWBAT2)
+#define MAX8998_MASK_LOWBAT1	(0x1 << MAX8998_SHIFT_LOWBAT1)
+
+/* STATUS2 */
+#define MAX8998_SHIFT_CHGDONE	6
+#define MAX8998_SHIFT_VDCIN	5
+#define MAX8998_SHIFT_DETBAT	4
+#define MAX8998_SHIFT_CHGON	3
+#define MAX8998_SHIFT_FCHG	2
+#define MAX8998_SHIFT_PQL	1
+
+#define MAX8998_MASK_CHGDONE	(0x1 << MAX8998_SHIFT_CHGDONE)
+#define MAX8998_MASK_VDCIN	(0x1 << MAX8998_SHIFT_VDCIN)
+#define MAX8998_MASK_DETBAT	(0x1 << MAX8998_SHIFT_DETBAT)
+#define MAX8998_MASK_CHGON	(0x1 << MAX8998_SHIFT_CHGON)
+#define MAX8998_MASK_FCHG	(0x1 << MAX8998_SHIFT_FCHG)
+#define MAX8998_MASK_PQL	(0x1 << MAX8998_SHIFT_PQL)
+
+/* CHGR1 */
+#define MAX8998_SHIFT_TOPOFF	5
+#define MAX8998_SHIFT_RSTR	3
+#define MAX8998_SHIFT_ICHG	0
+
+#define MAX8998_MASK_TOPOFF	(0x7 << MAX8998_SHIFT_TOPOFF)
+#define MAX8998_MASK_RSTR	(0x3 << MAX8998_SHIFT_RSTR)
+#define MAX8998_MASK_ICHG	(0x7 << MAX8998_SHIFT_ICHG)
+
+/* CHGR2 */
+#define MAX8998_SHIFT_ESAFEOUT	6
+#define MAX8998_SHIFT_FT	4
+#define MAX8998_SHIFT_BATTSL	3
+#define MAX8998_SHIFT_TMP	1
+#define MAX8998_SHIFT_CHGEN	0
+
+#define MAX8998_MASK_ESAFEOUT	(0x3 << MAX8998_SHIFT_ESAFEOUT)
+#define MAX8998_MASK_FT		(0x3 << MAX8998_SHIFT_FT)
+#define MAX8998_MASK_BATTSL	(0x1 << MAX8998_SHIFT_BATTSL)
+#define MAX8998_MASK_TMP	(0x3 << MAX8998_SHIFT_TMP)
+#define MAX8998_MASK_CHGEN	(0x1 << MAX8998_SHIFT_CHGEN)
+
+/* ONOFF1 */
+#define MAX8998_SHIFT_EN1	7
+#define MAX8998_SHIFT_EN2	6
+#define MAX8998_SHIFT_EN3	5
+#define MAX8998_SHIFT_EN4	4
+#define MAX8998_SHIFT_ELDO2	3
+#define MAX8998_SHIFT_ELDO3	2
+#define MAX8998_SHIFT_ELDO4	1
+#define MAX8998_SHIFT_ELDO5	0
+
+#define MAX8998_MASK_EN1	(0x1 << MAX8998_SHIFT_EN1)
+#define MAX8998_MASK_EN2	(0x1 << MAX8998_SHIFT_EN2)
+#define MAX8998_MASK_EN3	(0x1 << MAX8998_SHIFT_EN3)
+#define MAX8998_MASK_EN4	(0x1 << MAX8998_SHIFT_EN4)
+#define MAX8998_MASK_ELDO2	(0x1 << MAX8998_SHIFT_ELDO2)
+#define MAX8998_MASK_ELDO3	(0x1 << MAX8998_SHIFT_ELDO3)
+#define MAX8998_MASK_ELDO4	(0x1 << MAX8998_SHIFT_ELDO4)
+#define MAX8998_MASK_ELDO5	(0x1 << MAX8998_SHIFT_ELDO5)
+
+/* ONOFF2 */
+#define MAX8998_SHIFT_ELDO6	7
+#define MAX8998_SHIFT_ELDO7	6
+#define MAX8998_SHIFT_ELDO8	5
+#define MAX8998_SHIFT_ELDO9	4
+#define MAX8998_SHIFT_ELDO10	3
+#define MAX8998_SHIFT_ELDO11	2
+#define MAX8998_SHIFT_ELDO12	1
+#define MAX8998_SHIFT_ELDO13	0
+
+#define MAX8998_MASK_ELDO6	(0x1 << MAX8998_SHIFT_ELDO6)
+#define MAX8998_MASK_ELDO7	(0x1 << MAX8998_SHIFT_ELDO7)
+#define MAX8998_MASK_ELDO8	(0x1 << MAX8998_SHIFT_ELDO8)
+#define MAX8998_MASK_ELDO9	(0x1 << MAX8998_SHIFT_ELDO9)
+#define MAX8998_MASK_ELDO10	(0x1 << MAX8998_SHIFT_ELDO10)
+#define MAX8998_MASK_ELDO11	(0x1 << MAX8998_SHIFT_ELDO11)
+#define MAX8998_MASK_ELDO12	(0x1 << MAX8998_SHIFT_ELDO12)
+#define MAX8998_MASK_ELDO13	(0x1 << MAX8998_SHIFT_ELDO13)
+
+/* ONOFF3 */
+#define MAX8998_SHIFT_ELDO14	7
+#define MAX8998_SHIFT_ELDO15	6
+#define MAX8998_SHIFT_ELDO16	5
+#define MAX8998_SHIFT_ELDO17	4
+#define MAX8998_SHIFT_EPWRHOLD	3
+#define MAX8998_SHIFT_ENBATTMON	2
+#define MAX8998_SHIFT_ELBCNFG2	1
+#define MAX8998_SHIFT_ELBCNFG1	0
+
+#define MAX8998_MASK_ELDO14	(0x1 << MAX8998_SHIFT_ELDO14)
+#define MAX8998_MASK_ELDO15	(0x1 << MAX8998_SHIFT_ELDO15)
+#define MAX8998_MASK_ELDO16	(0x1 << MAX8998_SHIFT_ELDO16)
+#define MAX8998_MASK_ELDO17	(0x1 << MAX8998_SHIFT_ELDO17)
+#define MAX8998_MASK_EPWRHOLD	(0x1 << MAX8998_SHIFT_EPWRHOLD)
+#define MAX8998_MASK_ENBATTMON	(0x1 << MAX8998_SHIFT_ENBATTMON)
+#define MAX8998_MASK_ELBCNFG2	(0x1 << MAX8998_SHIFT_ELBCNFG2)
+#define MAX8998_MASK_ELBCNFG1	(0x1 << MAX8998_SHIFT_ELBCNFG1)
+
+/* ONOFF4 */
+#define MAX8998_SHIFT_EN32KHZAP	7
+#define MAX8998_SHIFT_EN32KHZCP	6
+#define MAX8998_SHIFT_ENVICHG	5
+#define MAX8998_SHIFT_ENRAMP	4
+#define MAX8998_SHIFT_RAMP	0
+
+#define MAX8998_MASK_EN32KHZAP	(0x1 << MAX8998_SHIFT_EN32KHZAP)
+#define MAX8998_MASK_EN32KHZCP	(0x1 << MAX8998_SHIFT_EN32KHZCP)
+#define MAX8998_MASK_ENVICHG	(0x1 << MAX8998_SHIFT_ENVICHG)
+#define MAX8998_MASK_ENRAMP	(0x1 << MAX8998_SHIFT_ENRAMP)
+#define MAX8998_MASK_RAMP	(0xF << MAX8998_SHIFT_RAMP)
+
 /**
  * struct max8998_dev - max8998 master device for sub-drivers
  * @dev: master device of the chip (can be used to access platform data)