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-rw-r--r--drivers/gpu/pvr/sgx/mmu.c8
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/gpu/pvr/sgx/mmu.c b/drivers/gpu/pvr/sgx/mmu.c
index c069bd8..d4c7e0b 100644
--- a/drivers/gpu/pvr/sgx/mmu.c
+++ b/drivers/gpu/pvr/sgx/mmu.c
@@ -200,8 +200,8 @@ static IMG_VOID PageTest(IMG_VOID* pMem, IMG_DEV_PHYADDR sDevPAddr);
#endif
#define PT_DUMP 1
-#define PT_DEBUG 0
+#define PT_DEBUG 0
#if (PT_DEBUG || PT_DUMP) && defined(PVRSRV_NEED_PVR_DPF)
static IMG_VOID DumpPT(MMU_PT_INFO *psPTInfoList)
{
@@ -748,10 +748,14 @@ _DeferredFreePageTable (MMU_HEAP *pMMUHeap, IMG_UINT32 ui32PTIndex, IMG_BOOL bOS
ppsPTInfoList = &pMMUHeap->psMMUContext->apsPTInfoList[ui32PDIndex];
{
+#if PT_DEBUG
if(ppsPTInfoList[ui32PTIndex] && ppsPTInfoList[ui32PTIndex]->ui32ValidPTECount > 0)
{
DumpPT(ppsPTInfoList[ui32PTIndex]);
+
}
+#endif
+
PVR_ASSERT(ppsPTInfoList[ui32PTIndex] == IMG_NULL || ppsPTInfoList[ui32PTIndex]->ui32ValidPTECount == 0);
}
@@ -2969,7 +2973,9 @@ MMU_MapPage (MMU_HEAP *pMMUHeap,
ui32Index ));
PVR_DPF((PVR_DBG_ERROR, "MMU_MapPage: Page table entry value: 0x%08X", uTmp));
PVR_DPF((PVR_DBG_ERROR, "MMU_MapPage: Physical page to map: 0x%08X", DevPAddr.uiAddr));
+#if PT_DUMP
DumpPT(ppsPTInfoList[0]);
+#endif
}
#if !defined(FIX_HW_BRN_31620)
PVR_ASSERT((uTmp & SGX_MMU_PTE_VALID) == 0);