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author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2013-09-21 11:23:50 +0100 |
---|---|---|
committer | Ziyan <jaraidaniel@gmail.com> | 2016-03-11 15:56:24 +0100 |
commit | e9e77491d75e8974046434209363190a433238e7 (patch) | |
tree | d497891a97a6a34d4592a80b072bf9aa8ad0182a | |
parent | 64526560de76ae1624ba652df8c499e7a1502953 (diff) | |
download | kernel_samsung_espresso10-e9e77491d75e8974046434209363190a433238e7.zip kernel_samsung_espresso10-e9e77491d75e8974046434209363190a433238e7.tar.gz kernel_samsung_espresso10-e9e77491d75e8974046434209363190a433238e7.tar.bz2 |
ARM: 7837/3: fix Thumb-2 bug in AES assembler code
commit 40190c85f427dcfdbab5dbef4ffd2510d649da1f upstream.
Patch 638591c enabled building the AES assembler code in Thumb2 mode.
However, this code used arithmetic involving PC rather than adr{l}
instructions to generate PC-relative references to the lookup tables,
and this needs to take into account the different PC offset when
running in Thumb mode.
Change-Id: I7358a145be3f37420c8ce5b8fc83a761b0d863ac
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r-- | arch/arm/crypto/aes-armv4.S | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/crypto/aes-armv4.S b/arch/arm/crypto/aes-armv4.S index 19d6cd6..3a14ea8 100644 --- a/arch/arm/crypto/aes-armv4.S +++ b/arch/arm/crypto/aes-armv4.S @@ -148,7 +148,7 @@ AES_Te: @ const AES_KEY *key) { .align 5 ENTRY(AES_encrypt) - sub r3,pc,#8 @ AES_encrypt + adr r3,AES_encrypt stmdb sp!,{r1,r4-r12,lr} mov r12,r0 @ inp mov r11,r2 @@ -381,7 +381,7 @@ _armv4_AES_encrypt: .align 5 ENTRY(private_AES_set_encrypt_key) _armv4_AES_set_encrypt_key: - sub r3,pc,#8 @ AES_set_encrypt_key + adr r3,_armv4_AES_set_encrypt_key teq r0,#0 moveq r0,#-1 beq .Labrt @@ -843,7 +843,7 @@ AES_Td: @ const AES_KEY *key) { .align 5 ENTRY(AES_decrypt) - sub r3,pc,#8 @ AES_decrypt + adr r3,AES_decrypt stmdb sp!,{r1,r4-r12,lr} mov r12,r0 @ inp mov r11,r2 |