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| author | Tony Luck <tony.luck@intel.com> | 2006-03-21 08:22:17 -0800 |
|---|---|---|
| committer | Tony Luck <tony.luck@intel.com> | 2006-03-21 08:22:17 -0800 |
| commit | ae02e964b669f19fb08d953032463ab7dc6f79eb (patch) | |
| tree | e02ff418110b06c5b7cac8302f9930573f2f35b0 /arch/ia64 | |
| parent | 409761bb6a06bd61e2d8e27a1af534371d9537ed (diff) | |
| parent | dcc1dd2366a7c355fd8b6543c52685b864a2044f (diff) | |
| download | kernel_samsung_espresso10-ae02e964b669f19fb08d953032463ab7dc6f79eb.zip kernel_samsung_espresso10-ae02e964b669f19fb08d953032463ab7dc6f79eb.tar.gz kernel_samsung_espresso10-ae02e964b669f19fb08d953032463ab7dc6f79eb.tar.bz2 | |
Pull icc-cleanup into release branch
Diffstat (limited to 'arch/ia64')
| -rw-r--r-- | arch/ia64/sn/kernel/Makefile | 3 | ||||
| -rw-r--r-- | arch/ia64/sn/kernel/pio_phys.S | 71 |
2 files changed, 73 insertions, 1 deletions
diff --git a/arch/ia64/sn/kernel/Makefile b/arch/ia64/sn/kernel/Makefile index 3e9b4ee..ab9c48c 100644 --- a/arch/ia64/sn/kernel/Makefile +++ b/arch/ia64/sn/kernel/Makefile @@ -10,7 +10,8 @@ CPPFLAGS += -I$(srctree)/arch/ia64/sn/include obj-y += setup.o bte.o bte_error.o irq.o mca.o idle.o \ - huberror.o io_init.o iomv.o klconflib.o sn2/ + huberror.o io_init.o iomv.o klconflib.o pio_phys.o \ + sn2/ obj-$(CONFIG_IA64_GENERIC) += machvec.o obj-$(CONFIG_SGI_TIOCX) += tiocx.o obj-$(CONFIG_IA64_SGI_SN_XP) += xp.o diff --git a/arch/ia64/sn/kernel/pio_phys.S b/arch/ia64/sn/kernel/pio_phys.S new file mode 100644 index 0000000..3c7d48d --- /dev/null +++ b/arch/ia64/sn/kernel/pio_phys.S @@ -0,0 +1,71 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2000-2005 Silicon Graphics, Inc. All rights reserved. + * + * This file contains macros used to access MMR registers via + * uncached physical addresses. + * pio_phys_read_mmr - read an MMR + * pio_phys_write_mmr - write an MMR + * pio_atomic_phys_write_mmrs - atomically write 1 or 2 MMRs with psr.ic=0 + * Second MMR will be skipped if address is NULL + * + * Addresses passed to these routines should be uncached physical addresses + * ie., 0x80000.... + */ + + + +#include <asm/asmmacro.h> +#include <asm/page.h> + +GLOBAL_ENTRY(pio_phys_read_mmr) + .prologue + .regstk 1,0,0,0 + .body + mov r2=psr + rsm psr.i | psr.dt + ;; + srlz.d + ld8.acq r8=[r32] + ;; + mov psr.l=r2;; + srlz.d + br.ret.sptk.many rp +END(pio_phys_read_mmr) + +GLOBAL_ENTRY(pio_phys_write_mmr) + .prologue + .regstk 2,0,0,0 + .body + mov r2=psr + rsm psr.i | psr.dt + ;; + srlz.d + st8.rel [r32]=r33 + ;; + mov psr.l=r2;; + srlz.d + br.ret.sptk.many rp +END(pio_phys_write_mmr) + +GLOBAL_ENTRY(pio_atomic_phys_write_mmrs) + .prologue + .regstk 4,0,0,0 + .body + mov r2=psr + cmp.ne p9,p0=r34,r0; + rsm psr.i | psr.dt | psr.ic + ;; + srlz.d + st8.rel [r32]=r33 +(p9) st8.rel [r34]=r35 + ;; + mov psr.l=r2;; + srlz.d + br.ret.sptk.many rp +END(pio_atomic_phys_write_mmrs) + + |