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| author | Greg Ungerer <gerg@uclinux.org> | 2010-11-09 14:27:50 +1000 |
|---|---|---|
| committer | Greg Ungerer <gerg@uclinux.org> | 2011-01-05 15:19:19 +1000 |
| commit | d475e3e4739ce465df740b51decbbea3b1b51823 (patch) | |
| tree | 537a24e871043cb216fe9db747e94367eca47a71 /arch/m68k/include | |
| parent | 8ce877a8eb8293b5b2c07f259d694026b0f519e4 (diff) | |
| download | kernel_samsung_espresso10-d475e3e4739ce465df740b51decbbea3b1b51823.zip kernel_samsung_espresso10-d475e3e4739ce465df740b51decbbea3b1b51823.tar.gz kernel_samsung_espresso10-d475e3e4739ce465df740b51decbbea3b1b51823.tar.bz2 | |
m68knommu: make cache push code ColdFire generic
Currently the code to push cache lines is only available to version 4
cores. Version 3 cores may also need to use this if we support copy-
back caches on them. Move this code to make it more generic, and
useful for all version ColdFire cores.
With this in place we can now have a single cache_flush_all() code
path that does all the right things on all version cores.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/m68k/include')
| -rw-r--r-- | arch/m68k/include/asm/cacheflush_no.h | 7 | ||||
| -rw-r--r-- | arch/m68k/include/asm/m54xxacr.h | 38 |
2 files changed, 7 insertions, 38 deletions
diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h index 8ada4ff..f931e18 100644 --- a/arch/m68k/include/asm/cacheflush_no.h +++ b/arch/m68k/include/asm/cacheflush_no.h @@ -30,9 +30,13 @@ #define copy_from_user_page(vma, page, vaddr, dst, src, len) \ memcpy(dst, src, len) -#ifndef __flush_cache_all +void mcf_cache_push(void); + static inline void __flush_cache_all(void) { +#ifdef CACHE_PUSH + mcf_cache_push(); +#endif #ifdef CACHE_INVALIDATE __asm__ __volatile__ ( "movel %0, %%d0\n\t" @@ -41,6 +45,5 @@ static inline void __flush_cache_all(void) : : "i" (CACHE_INVALIDATE) : "d0" ); #endif } -#endif /* __flush_cache_all */ #endif /* _M68KNOMMU_CACHEFLUSH_H */ diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h index 3c81a7a..6bce82f 100644 --- a/arch/m68k/include/asm/m54xxacr.h +++ b/arch/m68k/include/asm/m54xxacr.h @@ -83,46 +83,12 @@ #define ACR2_MODE (0x000f0000+INSN_CACHE_MODE) #define ACR3_MODE 0 -#ifndef __ASSEMBLY__ - #if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_WT) #define flush_dcache_range(a, l) do { asm("nop"); } while (0) #endif - -static inline void __m54xx_flush_cache_all(void) -{ - __asm__ __volatile__ ( #if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_CP) - /* - * Use cpushl to push and invalidate all cache lines. - * Gas doesn't seem to know how to generate the ColdFire - * cpushl instruction... Oh well, bit stuff it for now. - */ - "clrl %%d0\n\t" - "1:\n\t" - "movel %%d0,%%a0\n\t" - "2:\n\t" - ".word 0xf468\n\t" - "addl %0,%%a0\n\t" - "cmpl %1,%%a0\n\t" - "blt 2b\n\t" - "addql #1,%%d0\n\t" - "cmpil %2,%%d0\n\t" - "bne 1b\n\t" +/* Copyback cache mode must push dirty cache lines first */ +#define CACHE_PUSH #endif - "movel %3,%%d0\n\t" - "movec %%d0,%%CACR\n\t" - "nop\n\t" /* forces flush of Store Buffer */ - : /* No output */ - : "i" (CACHE_LINE_SIZE), - "i" (DCACHE_SIZE / CACHE_WAYS), - "i" (CACHE_WAYS), - "i" (CACHE_INVALIDATE) - : "d0", "a0" ); -} - -#define __flush_cache_all() __m54xx_flush_cache_all() - -#endif /* __ASSEMBLY__ */ #endif /* m54xxacr_h */ |