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| author | Ralf Baechle <ralf@linux-mips.org> | 2007-10-11 23:46:05 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2007-10-11 23:46:05 +0100 |
| commit | 641e97f318870921d048154af6807e46e43c307a (patch) | |
| tree | 6e0984a1bc8932db848be3fdb104a92c97fe341a /arch/mips/mm/cache.c | |
| parent | 424b28ba4d25fc41abdb7e6fa90e132f0d9558fb (diff) | |
| download | kernel_samsung_espresso10-641e97f318870921d048154af6807e46e43c307a.zip kernel_samsung_espresso10-641e97f318870921d048154af6807e46e43c307a.tar.gz kernel_samsung_espresso10-641e97f318870921d048154af6807e46e43c307a.tar.bz2 | |
[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.
It may not be perfect yet but the SB1 code is badly borken and has
horrible performance issues.
Downside: This seriously breaks support for pass 1 parts of the BCM1250
where indexed cacheops don't work quite reliable but I seem to be the
last one on the planet with a pass 1 part anyway.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm/cache.c')
| -rw-r--r-- | arch/mips/mm/cache.c | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index 81f925a..43dde87 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -3,13 +3,14 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1994 - 2003, 07 by Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 1994 - 2003, 06, 07 by Ralf Baechle (ralf@linux-mips.org) * Copyright (C) 2007 MIPS Technologies, Inc. */ #include <linux/fs.h> #include <linux/fcntl.h> #include <linux/init.h> #include <linux/kernel.h> +#include <linux/linkage.h> #include <linux/module.h> #include <linux/sched.h> #include <linux/mm.h> @@ -157,12 +158,6 @@ void __init cpu_cache_init(void) tx39_cache_init(); return; } - if (cpu_has_sb1_cache) { - extern void __weak sb1_cache_init(void); - - sb1_cache_init(); - return; - } panic(cache_panic); } |