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| author | Shinya Kuribayashi <shinya.kuribayashi@necel.com> | 2009-03-03 18:05:51 +0900 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2009-03-11 21:11:07 +0100 |
| commit | a644b2774d41409519bb33a16bd577cb41bb3095 (patch) | |
| tree | a0a8a574ac53e318dbf72306d6b752224ebdbc64 /arch/mips/mm | |
| parent | c189846ecf900cd6b3ad7d3cef5b45a746ce646b (diff) | |
| download | kernel_samsung_espresso10-a644b2774d41409519bb33a16bd577cb41bb3095.zip kernel_samsung_espresso10-a644b2774d41409519bb33a16bd577cb41bb3095.tar.gz kernel_samsung_espresso10-a644b2774d41409519bb33a16bd577cb41bb3095.tar.bz2 | |
MIPS: NEC VR5500 processor support fixup
Current VR5500 processor support lacks of some functions which are
expected to be configured/synthesized on arch initialization.
Here're some VR5500A spec notes:
* All execution hazards are handled in hardware.
* Once VR5500A stops the operation of the pipeline by WAIT instruction,
it could return from the standby mode only when either a reset, NMI
request, or all enabled interrupts is/are detected. In other words,
if interrupts are disabled by Status.IE=0, it keeps in standby mode
even when interrupts are internally asserted.
Notes on WAIT: The operation of the processor is undefined if WAIT
insn is in the branch delay slot. The operation is also undefined
if WAIT insn is executed when Status.EXL and Status.ERL are set to 1.
* VR5500A core only implements the Load prefetch.
With these changes, it boots fine.
Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm')
| -rw-r--r-- | arch/mips/mm/page.c | 3 | ||||
| -rw-r--r-- | arch/mips/mm/tlbex.c | 1 |
2 files changed, 3 insertions, 1 deletions
diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c index 1417c64..48060c6 100644 --- a/arch/mips/mm/page.c +++ b/arch/mips/mm/page.c @@ -172,8 +172,9 @@ static void __cpuinit set_prefetch_parameters(void) */ cache_line_size = cpu_dcache_line_size(); switch (current_cpu_type()) { + case CPU_R5500: case CPU_TX49XX: - /* TX49 supports only Pref_Load */ + /* These processors only support the Pref_Load. */ pref_bias_copy_load = 256; break; diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 4294203..f335cf6 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -318,6 +318,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, case CPU_BCM4710: case CPU_LOONGSON2: case CPU_CAVIUM_OCTEON: + case CPU_R5500: if (m4kc_tlbp_war()) uasm_i_nop(p); tlbw(p); |