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| author | Ralf Baechle <ralf@linux-mips.org> | 2005-07-14 15:57:16 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2005-10-29 19:31:53 +0100 |
| commit | e01402b115cccb6357f956649487aca2c6f7fbba (patch) | |
| tree | 256e14f8d2762de98b992219b1a47e8f56b4b0da /arch/mips/mm | |
| parent | 86071b637db7baf599df26fdf820dce2fc55ca9f (diff) | |
| download | kernel_samsung_espresso10-e01402b115cccb6357f956649487aca2c6f7fbba.zip kernel_samsung_espresso10-e01402b115cccb6357f956649487aca2c6f7fbba.tar.gz kernel_samsung_espresso10-e01402b115cccb6357f956649487aca2c6f7fbba.tar.bz2 | |
More AP / SP bits for the 34K, the Malta bits and things. Still wants
a little polishing.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm')
| -rw-r--r-- | arch/mips/mm/c-r4k.c | 3 | ||||
| -rw-r--r-- | arch/mips/mm/c-sb1.c | 5 |
2 files changed, 3 insertions, 5 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index d3e352f..6a1267a 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1228,8 +1228,7 @@ void __init ld_mmu_r4xx0(void) struct cpuinfo_mips *c = ¤t_cpu_data; /* Default cache error handler for R4000 and R5000 family */ - memcpy((void *)(CAC_BASE + 0x100), &except_vec2_generic, 0x80); - memcpy((void *)(UNCAC_BASE + 0x100), &except_vec2_generic, 0x80); + set_uncached_handler (0x100, &except_vec2_generic, 0x80); probe_pcache(); setup_scache(); diff --git a/arch/mips/mm/c-sb1.c b/arch/mips/mm/c-sb1.c index e65b1bb..d183dbc 100644 --- a/arch/mips/mm/c-sb1.c +++ b/arch/mips/mm/c-sb1.c @@ -502,9 +502,8 @@ void ld_mmu_sb1(void) extern char handle_vec2_sb1; /* Special cache error handler for SB1 */ - memcpy((void *)(CAC_BASE + 0x100), &except_vec2_sb1, 0x80); - memcpy((void *)(UNCAC_BASE + 0x100), &except_vec2_sb1, 0x80); - memcpy((void *)CKSEG1ADDR(&handle_vec2_sb1), &handle_vec2_sb1, 0x80); + set_uncached_handler (0x100, &except_vec2_sb1, 0x80); + memcpy((void *)KSEG1ADDR(&handle_vec2_sb1), &handle_vec2_sb1, 0x80); probe_cache_sizes(); |