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authorThomas Gleixner <tglx@linutronix.de>2011-03-17 19:32:58 +0000
committerGrant Likely <grant.likely@secretlab.ca>2011-03-17 23:07:44 -0600
commit84bead6c38b0374e6e7db06b3097f0e700b8f148 (patch)
treed2570d9265aaea5f2b4df6b7bba44f390687f031 /drivers/gpio
parent732063b92bb727b27e61580ce278dddefe31c6ad (diff)
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gpio/langwell: Clear edge bit before handling
I don't have the specs for this beast, but it looks a lot like the PXA GPIO block. Though I bet it's the same IP and the driver should have reused the PXA code. Acknowleding the edge detect status after handling one or more gpio interrupts looks wrong. We might lose an edge which came in while we handled the previous one. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Alek Du <alek.du@intel.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'drivers/gpio')
-rw-r--r--drivers/gpio/langwell_gpio.c13
1 files changed, 6 insertions, 7 deletions
diff --git a/drivers/gpio/langwell_gpio.c b/drivers/gpio/langwell_gpio.c
index f658af0..560ab64 100644
--- a/drivers/gpio/langwell_gpio.c
+++ b/drivers/gpio/langwell_gpio.c
@@ -190,23 +190,22 @@ static void lnw_irq_handler(unsigned irq, struct irq_desc *desc)
struct irq_data *data = irq_desc_get_irq_data(desc);
struct lnw_gpio *lnw = irq_data_get_irq_handler_data(data);
struct irq_chip *chip = irq_data_get_irq_chip(data);
- u32 base, gpio, gedr_v;
+ u32 base, gpio, mask;
unsigned long pending;
void __iomem *gedr;
/* check GPIO controller to check which pin triggered the interrupt */
for (base = 0; base < lnw->chip.ngpio; base += 32) {
gedr = gpio_reg(&lnw->chip, base, GEDR);
- gedr_v = pending = readl(gedr);
- if (!gedr_v)
- continue;
+ pending = readl(gedr);
while (pending) {
gpio = __ffs(pending) - 1;
- pending &= ~BIT(gpio);
+ mask = BIT(gpio);
+ pending &= ~mask;
+ /* Clear before handling so we can't lose an edge */
+ writel(mask, gedr);
generic_handle_irq(lnw->irq_base + base + gpio);
}
- /* clear the edge detect status bit */
- writel(gedr_v, gedr);
}
chip->irq_eoi(data);