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| author | Dmitry Kravkov <dmitry@broadcom.com> | 2011-09-22 02:33:31 +0000 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2011-10-03 11:41:12 -0700 |
| commit | e69f24bc82f6cc28f7df885d401bc79ff3dc6401 (patch) | |
| tree | cffc2a7dfb042e38c3645d282cc947a3f749f2f6 /drivers/net/bnx2x/bnx2x_reg.h | |
| parent | 3c1c4f8e80a39ae7d6d2a159e3b28f742fd4e968 (diff) | |
| download | kernel_samsung_espresso10-e69f24bc82f6cc28f7df885d401bc79ff3dc6401.zip kernel_samsung_espresso10-e69f24bc82f6cc28f7df885d401bc79ff3dc6401.tar.gz kernel_samsung_espresso10-e69f24bc82f6cc28f7df885d401bc79ff3dc6401.tar.bz2 | |
bnx2x: fix hw attention handling
commit f2eaeb58bf6995a979c413ea0cc73289533feacb upstream.
Use register name to initialize attention mask
Signed-off-by: Dmitry Kravkov <dmitry@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/net/bnx2x/bnx2x_reg.h')
| -rw-r--r-- | drivers/net/bnx2x/bnx2x_reg.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/net/bnx2x/bnx2x_reg.h b/drivers/net/bnx2x/bnx2x_reg.h index 86bba25..0380b3a 100644 --- a/drivers/net/bnx2x/bnx2x_reg.h +++ b/drivers/net/bnx2x/bnx2x_reg.h @@ -1325,6 +1325,18 @@ Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ #define MISC_REG_AEU_ENABLE4_PXP_0 0xa108 #define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8 +/* [RW 32] fifth 32b for enabling the output for function 0 output0. Mapped + * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC + * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] + * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 + * parity; [31-10] Reserved; */ +#define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0 0xa688 +/* [RW 32] Fifth 32b for enabling the output for function 1 output0. Mapped + * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC + * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] + * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 + * parity; [31-10] Reserved; */ +#define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 0xa6b0 /* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu 128 bit vector */ #define MISC_REG_AEU_GENERAL_ATTN_0 0xa000 |