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| author | Neil Horman <nhorman@tuxdriver.com> | 2010-12-08 09:47:48 -0500 |
|---|---|---|
| committer | Jesse Barnes <jbarnes@virtuousgeek.org> | 2010-12-16 14:07:31 -0800 |
| commit | 49c2fa08a77a7eefa4cbc73601f64984aceacfa7 (patch) | |
| tree | 78e9629014dcaf5922606b7ff1c6049cbed78716 /drivers/pci | |
| parent | 6313e3c21743cc88bb5bd8aa72948ee1e83937b6 (diff) | |
| download | kernel_samsung_espresso10-49c2fa08a77a7eefa4cbc73601f64984aceacfa7.zip kernel_samsung_espresso10-49c2fa08a77a7eefa4cbc73601f64984aceacfa7.tar.gz kernel_samsung_espresso10-49c2fa08a77a7eefa4cbc73601f64984aceacfa7.tar.bz2 | |
PCI: Update MCP55 quirk to not affect non HyperTransport variants
I wrote this quirk awhile ago to properly setup MCP55 chips on hypertransport
busses so that interrupts reached whatever cpu happend to boot the kdump kernel.
while that works well, it was recently shown to me that a a non-hypertransport
variant of the MCP55 exists, and on those system the register that this quirk
manipulates causes hangs if you write to it. Since the quirk was only meant to
handle errors found on MCP55 chips that have a HT interface, this patch adds a
filter to make sure the chip is an HT capable before making the needed register
adjustment. This lets the broken MCP55s work with kdump while not breaking the
non-HT variants.
Resolves https://bugzilla.kernel.org/show_bug.cgi?id=23952
Tested successfully by the reporter and myself.
Cc: stable@kernel.org
Reported-by: Mathieu Bérard <mathieu@mberard.eu>
Acked-by: Vivek Goyal <vgoyal@redhat.com>
Signed-off-by: Neil Horman <nhorman@tuxdriver.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/quirks.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 6f9350c..313c0bd 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -2329,6 +2329,9 @@ static void __devinit nvbridge_check_legacy_irq_routing(struct pci_dev *dev) { u32 cfg; + if (!pci_find_capability(dev, PCI_CAP_ID_HT)) + return; + pci_read_config_dword(dev, 0x74, &cfg); if (cfg & ((1 << 2) | (1 << 15))) { |