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authorMike Miller <mike.miller@hp.com>2008-03-04 11:25:15 +0100
committerJens Axboe <jens.axboe@oracle.com>2008-03-04 11:28:43 +0100
commit68d95b585f1b67b3c89ce0eb934e221ebeeb5c61 (patch)
treea039e77970aa5ed39902dfeeed41df2db3f7f2c4 /drivers
parentecb80c6a490863af569853eea2a925f97e9e856a (diff)
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cciss: remove READ_AHEAD define and use block layer defaults
This patch removes the #define READ_AHEAD 1024 from the driver and uses the block layer defaults, instead. We have found that under certain workloads the setting can cause a disk connected to the e200 controller to go offline. If the disk hiccups the link may try to downshift but the controller is never notified that the link successfully completed the renegotiation. We've also found that performance using the block layer default of 32 pages was on par with the 1024 setting. We tried setting it to zero at one time based on info from our firmware guys but that killed performance. Turns out we were talking about 2 different read ahead settings. Please consider this for inclusion. Signed-off-by: Mike Miller <mike.miller@hp.com> Signed-off-by: Jens Axboe <jens.axboe@oracle.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/block/cciss.c3
1 files changed, 0 insertions, 3 deletions
diff --git a/drivers/block/cciss.c b/drivers/block/cciss.c
index f1e7390..55bd35c 100644
--- a/drivers/block/cciss.c
+++ b/drivers/block/cciss.c
@@ -132,7 +132,6 @@ static struct board_type products[] = {
/*define how many times we will try a command because of bus resets */
#define MAX_CMD_RETRIES 3
-#define READ_AHEAD 1024
#define MAX_CTLR 32
/* Originally cciss driver only supports 8 major numbers */
@@ -1402,7 +1401,6 @@ geo_inq:
disk->private_data = &h->drv[drv_index];
/* Set up queue information */
- disk->queue->backing_dev_info.ra_pages = READ_AHEAD;
blk_queue_bounce_limit(disk->queue, hba[ctlr]->pdev->dma_mask);
/* This is a hardware imposed limit. */
@@ -3495,7 +3493,6 @@ static int __devinit cciss_init_one(struct pci_dev *pdev,
}
drv->queue = q;
- q->backing_dev_info.ra_pages = READ_AHEAD;
blk_queue_bounce_limit(q, hba[i]->pdev->dma_mask);
/* This is a hardware imposed limit. */