Merge branch wuxga/p-android-omap-3.0-dev into p-android-omap-3.0-dev

Change-Id: I695b59aeccd2e5cb5a50c6fc734c5d54795f5615
Signed-off-by: Dima Svetlov <svetlov@ti.com>

2 files changed, 102 insertions, 0 deletions

diff --git a/include/video/dsscomp.h b/include/video/dsscomp.h
index 2d5e9dc..c5f8ec9 100644
--- a/include/video/dsscomp.h
+++ b/include/video/dsscomp.h
@@ -632,6 +632,52 @@ struct dsscomp_wait_data {
 	enum dsscomp_wait_phase phase;	/* phase to wait for */
 };
 
+enum dsscomp_fbmem_type {
+	DSSCOMP_FBMEM_TILER2D = 0,
+	DSSCOMP_FBMEM_VRAM = 1,
+};
+
+/*
+ * ioctl: DSSCIOC_QUERY_PLATFORM, struct dsscomp_platform_info
+ *
+ * Use this ioctl to get platform information needed to decide
+ * DSS/DSSCOMP capabilities, by filling out the passed structure with:
+ *
+ * A) predecimation limits
+ * B) maximum fclk (DSS is assumed to scale up to this fclk automatically
+ *    to support frames)
+ * C) minimum and maximum sizes (for now we use the same limits for
+ *    both source and window sizes, which works for OMAP4/5)
+ * D) scaler limitations. (assuming same max downscale limitation both
+ *    horizontally/vertically; however, fclock requirements are only
+ *    dependent on horizontal scaling, which works for OMAP4 ES1.1+ and
+ *    OMAP5 only).
+ *    integer_scale_ratio_limit is the maximum source width to round up
+ *    fclock/pixclock to an integer.
+ * E) Tiler1D slot size
+ *
+ * Returns: 0 on success, <0 error value on failure (unlikely)
+ */
+
+struct dsscomp_platform_info {
+	/* decimation limits for 2D and 1D buffers */
+	__u8 max_xdecim_2d;
+	__u8 max_ydecim_2d;
+	__u8 max_xdecim_1d;
+	__u8 max_ydecim_1d;
+	__u32 fclk;		/* dispc max fclk */
+	/* pipeline source/destination limits */
+	__u8 min_width;
+	__u16 max_width;
+	__u16 max_height;
+	/* scaler limitations */
+	__u8 max_downscale;
+	/* below this width, we assume integer pixelclk scale */
+	__u16 integer_scale_ratio_limit;
+	__u32 tiler1d_slot_size;
+	enum dsscomp_fbmem_type fbmem_type; /* TILER2D vs VRAM */
+};
+
 /* IOCTLS */
 #define DSSCIOC_SETUP_MGR	_IOW('O', 128, struct dsscomp_setup_mgr_data)
 #define DSSCIOC_CHECK_OVL	_IOWR('O', 129, struct dsscomp_check_ovl_data)
@@ -641,4 +687,5 @@ struct dsscomp_wait_data {
 
 #define DSSCIOC_SETUP_DISPC	_IOW('O', 133, struct dsscomp_setup_dispc_data)
 #define DSSCIOC_SETUP_DISPLAY	_IOW('O', 134, struct dsscomp_setup_display_data)
+#define DSSCIOC_QUERY_PLATFORM	_IOR('O', 135, struct dsscomp_platform_info)
 #endif
diff --git a/include/video/omapdss.h b/include/video/omapdss.h
index 9563a1f..1e97051 100644
--- a/include/video/omapdss.h
+++ b/include/video/omapdss.h
@@ -326,6 +326,45 @@ struct omap_video_timings {
 	u16 vbp;	/* Vertical back porch */
 };
 
+struct omap_dsi_timings {
+	/* Unit: HS DSI byte clocks */
+	u16 tl;		/* Total line length */
+	/* Unit: pixels */
+	u16 vact;	/* Active lines */
+	/* Unit: HS DSI byte clocks */
+	u16 hsa;	/* Horizontal synchronization pulse width */
+	/* Unit: HS DSI byte clocks */
+	u16 hfp;	/* Horizontal front porch */
+	/* Unit: HS DSI byte clocks */
+	u16 hbp;	/* Horizontal back porch */
+	/* Unit: Line clocks */
+	u16 vsa;	/* Vertical synchronization pulse width */
+	/* Unit: Line clocks */
+	u16 vfp;	/* Vertical front porch */
+	/* Unit: Line clocks */
+	u16 vbp;	/* Vertical back porch */
+	/* Unit: HS DSI byte clocks */
+	u16 hsa_hs_int;	/* HSA HS interleaving */
+	/* Unit: HS DSI byte clocks */
+	u16 hfp_hs_int;	/* HFP HS interleaving */
+	/* Unit: HS DSI byte clocks */
+	u16 hbp_hs_int;	/* HBP HS interleaving */
+	/* Unit: DSI Command mode packets */
+	u16 hsa_lp_int;	/* HSA LP interleaving */
+	/* Unit: DSI Command mode packets */
+	u16 hfp_lp_int;	/* HFP LP interleaving */
+	/* Unit: DSI Command mode packets */
+	u16 hbp_lp_int;	/* HBP LP interleaving */
+	/* Unit: HS DSI byte clocks */
+	u16 bl_hs_int;	/* Blanking HS interleaving */
+	/* Unit: DSI command mode packets */
+	u16 bl_lp_int;	/* Blanking LP interleaving */
+	/* Unit: HS DSI byte clocks */
+	u16 enter_lat;	/* Enter HS mode latency */
+	/* Unit: HS DSI byte clocks */
+	u16 exit_lat;	/* Exit HS mode latency */
+};
+
 #ifdef CONFIG_OMAP2_DSS_VENC
 /* Hardcoded timings for tv modes. Venc only uses these to
  * identify the mode, and does not actually use the configs
@@ -582,6 +621,7 @@ struct omap_dss_device {
 
 			bool ext_te;
 			u8 ext_te_gpio;
+			u8 line_bufs;
 		} dsi;
 
 		struct {
@@ -610,6 +650,18 @@ struct omap_dss_device {
 			u16 lp_clk_div;
 			unsigned offset_ddr_clk;
 			enum omap_dss_clk_source dsi_fclk_src;
+			u8 tlpx;
+			struct {
+				u8 zero;
+				u8 prepare;
+				u8 trail;
+			} tclk;
+			struct {
+				u8 zero;
+				u8 prepare;
+				u8 trail;
+				u8 exit;
+			} ths;
 		} dsi;
 
 		struct {
@@ -671,6 +723,9 @@ struct omap_dss_device {
 	void (*platform_disable)(struct omap_dss_device *dssdev);
 	int (*set_backlight)(struct omap_dss_device *dssdev, int level);
 	int (*get_backlight)(struct omap_dss_device *dssdev);
+
+	struct omap_video_timings *dispc_timings;
+	struct omap_dsi_timings *dsi_timings;
 };
 
 struct omap_dss_driver {