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-rw-r--r--arch/arm/mach-ux500/include/mach/gpio.h12
-rw-r--r--arch/arm/mach-ux500/include/mach/hardware.h12
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs.h8
3 files changed, 31 insertions, 1 deletions
diff --git a/arch/arm/mach-ux500/include/mach/gpio.h b/arch/arm/mach-ux500/include/mach/gpio.h
new file mode 100644
index 0000000..3c4cd31
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/gpio.h
@@ -0,0 +1,12 @@
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H
+
+/*
+ * 288 (#267 is the highest one actually hooked up) onchip GPIOs, plus enough
+ * room for a couple of GPIO expanders.
+ */
+#define ARCH_NR_GPIOS 350
+
+#include <plat/gpio.h>
+
+#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h
index f29a43d..99ca89f 100644
--- a/arch/arm/mach-ux500/include/mach/hardware.h
+++ b/arch/arm/mach-ux500/include/mach/hardware.h
@@ -23,6 +23,8 @@
/* typesafe io address */
#define __io_address(n) __io(IO_ADDRESS(n))
+/* used by some plat-nomadik code */
+#define io_p2v(n) __io_address(n)
/*
* Base address definitions for U8500 Onchip IPs. All the
@@ -128,6 +130,16 @@
#define U8500_GPIO1_BASE (U8500_PER1_BASE + 0xe000)
#define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000)
+#define U8500_GPIOBANK0_BASE U8500_GPIO1_BASE
+#define U8500_GPIOBANK1_BASE (U8500_GPIO1_BASE + 0x80)
+#define U8500_GPIOBANK2_BASE U8500_GPIO3_BASE
+#define U8500_GPIOBANK3_BASE (U8500_GPIO3_BASE + 0x80)
+#define U8500_GPIOBANK4_BASE (U8500_GPIO3_BASE + 0x100)
+#define U8500_GPIOBANK5_BASE (U8500_GPIO3_BASE + 0x180)
+#define U8500_GPIOBANK6_BASE U8500_GPIO2_BASE
+#define U8500_GPIOBANK7_BASE (U8500_GPIO2_BASE + 0x80)
+#define U8500_GPIOBANK8_BASE U8500_GPIO5_BASE
+
/* ST-Ericsson modified pl022 id */
#define SSP_PER_ID 0x01080022
diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h
index 394b5dd..8a1f697 100644
--- a/arch/arm/mach-ux500/include/mach/irqs.h
+++ b/arch/arm/mach-ux500/include/mach/irqs.h
@@ -66,6 +66,12 @@
/* There are 128 shared peripheral interrupts assigned to
* INTID[160:32]. The first 32 interrupts are reserved.
*/
-#define NR_IRQS 161
+#define U8500_SOC_NR_IRQS 161
+
+/* After chip-specific IRQ numbers we have the GPIO ones */
+#define NOMADIK_NR_GPIO 288
+#define NOMADIK_GPIO_TO_IRQ(gpio) ((gpio) + U8500_SOC_NR_IRQS)
+#define NOMADIK_IRQ_TO_GPIO(irq) ((irq) - U8500_SOC_NR_IRQS)
+#define NR_IRQS NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO)
#endif /*ASM_ARCH_IRQS_H*/