diff options
Diffstat (limited to 'arch/xtensa')
30 files changed, 290 insertions, 915 deletions
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 9eccfbd..2e74cb0 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -48,25 +48,10 @@ menu "Processor type and features" choice prompt "Xtensa Processor Configuration" - default XTENSA_CPU_LINUX_BE + default XTENSA_VARIANT_FSF -config XTENSA_CPU_LINUX_BE - bool "linux_be" - ---help--- - The linux_be processor configuration is the baseline Xtensa - configurations included in this kernel and also used by - binutils, gcc, and gdb. It contains no TIE, no coprocessors, - and the following configuration options: - - Code Density Option 2 Misc Special Registers - NSA/NSAU Instructions 128-bit Data Bus Width - Processor ID 8K, 2-way I and D Caches - Zero-Overhead Loops 2 Inst Address Break Registers - Big Endian 2 Data Address Break Registers - 64 General-Purpose Registers JTAG Interface and Trace Port - 17 Interrupts MMU w/ TLBs and Autorefill - 3 Interrupt Levels 8 Autorefill Ways (I/D TLBs) - 3 Timers Unaligned Exceptions +config XTENSA_VARIANT_FSF + bool "fsf" endchoice config MMU diff --git a/arch/xtensa/Makefile b/arch/xtensa/Makefile index 3a3a4c6..95f836d 100644 --- a/arch/xtensa/Makefile +++ b/arch/xtensa/Makefile @@ -11,13 +11,13 @@ # this architecture # Core configuration. -# (Use CPU=<xtensa_config> to use another default compiler.) +# (Use VAR=<xtensa_config> to use another default compiler.) -cpu-$(CONFIG_XTENSA_CPU_LINUX_BE) := linux_be -cpu-$(CONFIG_XTENSA_CPU_LINUX_CUSTOM) := linux_custom +variant-$(CONFIG_XTENSA_VARIANT_FSF) := fsf +variant-$(CONFIG_XTENSA_VARIANT_LINUX_CUSTOM) := custom -CPU = $(cpu-y) -export CPU +VARIANT = $(variant-y) +export VARIANT # Platform configuration @@ -27,8 +27,6 @@ platform-$(CONFIG_XTENSA_PLATFORM_ISS) := iss PLATFORM = $(platform-y) export PLATFORM -CPPFLAGS += $(if $(KBUILD_SRC),-I$(srctree)/include/asm-xtensa/) -CPPFLAGS += -Iinclude/asm CFLAGS += -pipe -mlongcalls KBUILD_DEFCONFIG := iss_defconfig @@ -41,12 +39,12 @@ core-$(CONFIG_EMBEDDED_RAMDISK) += arch/xtensa/boot/ramdisk/ # Test for cross compiling -ifneq ($(CPU),) +ifneq ($(VARIANT),) COMPILE_ARCH = $(shell uname -m) ifneq ($(COMPILE_ARCH), xtensa) ifndef CROSS_COMPILE - CROSS_COMPILE = xtensa_$(CPU)- + CROSS_COMPILE = xtensa_$(VARIANT)- endif endif endif @@ -68,14 +66,13 @@ archinc := include/asm-xtensa archprepare: $(archinc)/.platform -# Update machine cpu and platform symlinks if something which affects +# Update processor variant and platform symlinks if something which affects # them changed. $(archinc)/.platform: $(wildcard include/config/arch/*.h) include/config/auto.conf - @echo ' SYMLINK $(archinc)/xtensa/config -> $(archinc)/xtensa/config-$(CPU)' + @echo ' SYMLINK $(archinc)/variant -> $(archinc)/variant-$(VARIANT)' $(Q)mkdir -p $(archinc) - $(Q)mkdir -p $(archinc)/xtensa - $(Q)ln -fsn $(srctree)/$(archinc)/xtensa/config-$(CPU) $(archinc)/xtensa/config + $(Q)ln -fsn $(srctree)/$(archinc)/variant-$(VARIANT) $(archinc)/variant @echo ' SYMLINK $(archinc)/platform -> $(archinc)/platform-$(PLATFORM)' $(Q)ln -fsn $(srctree)/$(archinc)/platform-$(PLATFORM) $(archinc)/platform @touch $@ @@ -89,7 +86,7 @@ zImage zImage.initrd: vmlinux $(Q)$(MAKE) $(build)=$(boot) $@ CLEAN_FILES += arch/xtensa/vmlinux.lds \ - $(archinc)/platform $(archinc)/xtensa/config \ + $(archinc)/platform $(archinc)/variant \ $(archinc)/.platform define archhelp diff --git a/arch/xtensa/boot/boot-elf/bootstrap.S b/arch/xtensa/boot/boot-elf/bootstrap.S index f857fc7..464298b 100644 --- a/arch/xtensa/boot/boot-elf/bootstrap.S +++ b/arch/xtensa/boot/boot-elf/bootstrap.S @@ -1,7 +1,4 @@ -#include <xtensa/config/specreg.h> -#include <xtensa/config/core.h> - #include <asm/bootparam.h> diff --git a/arch/xtensa/boot/boot-redboot/bootstrap.S b/arch/xtensa/boot/boot-redboot/bootstrap.S index ee636b0..8484812 100644 --- a/arch/xtensa/boot/boot-redboot/bootstrap.S +++ b/arch/xtensa/boot/boot-redboot/bootstrap.S @@ -1,9 +1,7 @@ - -#define _ASMLANGUAGE -#include <xtensa/config/specreg.h> -#include <xtensa/config/core.h> -#include <xtensa/cacheasm.h> - +#include <asm/variant/core.h> +#include <asm/regs.h> +#include <asm/asmmacro.h> +#include <asm/cacheasm.h> /* * RB-Data: RedBoot data/bss * P: Boot-Parameters @@ -77,8 +75,14 @@ _start: /* Note: The assembler cannot relax "addi a0, a0, ..." to an l32r, so we load to a4 first. */ - addi a4, a0, __start - __start_a0 - mov a0, a4 + # addi a4, a0, __start - __start_a0 + # mov a0, a4 + + movi a4, __start + movi a5, __start_a0 + add a4, a0, a4 + sub a0, a4, a5 + movi a4, __start movi a5, __reloc_end @@ -106,9 +110,13 @@ _start: /* We have to flush and invalidate the caches here before we jump. */ #if XCHAL_DCACHE_IS_WRITEBACK - dcache_writeback_all a5, a6 + + ___flush_dcache_all a5 a6 + #endif - icache_invalidate_all a5, a6 + + ___invalidate_icache_all a5 a6 + isync movi a11, _reloc jx a11 @@ -209,9 +217,14 @@ _reloc: /* jump to the kernel */ 2: #if XCHAL_DCACHE_IS_WRITEBACK - dcache_writeback_all a5, a6 + + ___flush_dcache_all a5 a6 + #endif - icache_invalidate_all a5, a6 + + ___invalidate_icache_all a5 a6 + + isync movi a5, __start movi a3, boot_initrd_start diff --git a/arch/xtensa/configs/iss_defconfig b/arch/xtensa/configs/iss_defconfig index 802621d..f198540 100644 --- a/arch/xtensa/configs/iss_defconfig +++ b/arch/xtensa/configs/iss_defconfig @@ -53,11 +53,7 @@ CONFIG_CC_ALIGN_JUMPS=0 # # Processor type and features # -CONFIG_XTENSA_ARCH_LINUX_BE=y -# CONFIG_XTENSA_ARCH_LINUX_LE is not set -# CONFIG_XTENSA_ARCH_LINUX_TEST is not set -# CONFIG_XTENSA_ARCH_S5 is not set -# CONFIG_XTENSA_CUSTOM is not set +CONFIG_XTENSA_VARIANT_FSF=y CONFIG_MMU=y # CONFIG_XTENSA_UNALIGNED_USER is not set # CONFIG_PREEMPT is not set diff --git a/arch/xtensa/kernel/align.S b/arch/xtensa/kernel/align.S index a495657..33d6e9d 100644 --- a/arch/xtensa/kernel/align.S +++ b/arch/xtensa/kernel/align.S @@ -16,14 +16,9 @@ */ #include <linux/linkage.h> -#include <asm/ptrace.h> -#include <asm/ptrace.h> #include <asm/current.h> #include <asm/asm-offsets.h> -#include <asm/pgtable.h> #include <asm/processor.h> -#include <asm/page.h> -#include <asm/thread_info.h> #if XCHAL_UNALIGNED_LOAD_EXCEPTION || XCHAL_UNALIGNED_STORE_EXCEPTION @@ -216,7 +211,7 @@ ENTRY(fast_unaligned) extui a5, a4, INSN_OP0, 4 # get insn.op0 nibble -#if XCHAL_HAVE_NARROW +#if XCHAL_HAVE_DENSITY _beqi a5, OP0_L32I_N, .Lload # L32I.N, jump addi a6, a5, -OP0_S32I_N _beqz a6, .Lstore # S32I.N, do a store @@ -251,7 +246,7 @@ ENTRY(fast_unaligned) #endif __src_b a3, a5, a6 # a3 has the data word -#if XCHAL_HAVE_NARROW +#if XCHAL_HAVE_DENSITY addi a7, a7, 2 # increment PC (assume 16-bit insn) extui a5, a4, INSN_OP0, 4 @@ -279,14 +274,14 @@ ENTRY(fast_unaligned) 1: -#if XCHAL_HAVE_LOOP - rsr a3, LEND # check if we reached LEND - bne a7, a3, 1f - rsr a3, LCOUNT # and LCOUNT != 0 - beqz a3, 1f - addi a3, a3, -1 # decrement LCOUNT and set +#if XCHAL_HAVE_LOOPS + rsr a5, LEND # check if we reached LEND + bne a7, a5, 1f + rsr a5, LCOUNT # and LCOUNT != 0 + beqz a5, 1f + addi a5, a5, -1 # decrement LCOUNT and set rsr a7, LBEG # set PC to LBEGIN - wsr a3, LCOUNT + wsr a5, LCOUNT #endif 1: wsr a7, EPC_1 # skip load instruction @@ -336,7 +331,7 @@ ENTRY(fast_unaligned) movi a6, 0 # mask: ffffffff:00000000 -#if XCHAL_HAVE_NARROW +#if XCHAL_HAVE_DENSITY addi a7, a7, 2 # incr. PC,assume 16-bit instruction extui a5, a4, INSN_OP0, 4 # extract OP0 @@ -359,14 +354,14 @@ ENTRY(fast_unaligned) /* Get memory address */ 1: -#if XCHAL_HAVE_LOOP - rsr a3, LEND # check if we reached LEND - bne a7, a3, 1f - rsr a3, LCOUNT # and LCOUNT != 0 - beqz a3, 1f - addi a3, a3, -1 # decrement LCOUNT and set +#if XCHAL_HAVE_LOOPS + rsr a4, LEND # check if we reached LEND + bne a7, a4, 1f + rsr a4, LCOUNT # and LCOUNT != 0 + beqz a4, 1f + addi a4, a4, -1 # decrement LCOUNT and set rsr a7, LBEG # set PC to LBEGIN - wsr a3, LCOUNT + wsr a4, LCOUNT #endif 1: wsr a7, EPC_1 # skip store instruction @@ -416,6 +411,7 @@ ENTRY(fast_unaligned) /* Restore working register */ + l32i a8, a2, PT_AREG8 l32i a7, a2, PT_AREG7 l32i a6, a2, PT_AREG6 l32i a5, a2, PT_AREG5 @@ -446,7 +442,7 @@ ENTRY(fast_unaligned) mov a1, a2 rsr a0, PS - bbsi.l a2, PS_UM_SHIFT, 1f # jump if user mode + bbsi.l a2, PS_UM_BIT, 1f # jump if user mode movi a0, _kernel_exception jx a0 diff --git a/arch/xtensa/kernel/coprocessor.S b/arch/xtensa/kernel/coprocessor.S index cf5a93f..01bcb9f 100644 --- a/arch/xtensa/kernel/coprocessor.S +++ b/arch/xtensa/kernel/coprocessor.S @@ -90,7 +90,6 @@ ENTRY(enable_coprocessor) rsync retw -#endif ENTRY(save_coprocessor_extra) entry sp, 16 @@ -197,4 +196,5 @@ _xtensa_reginfo_tables: XCHAL_CP7_SA_CONTENTS_LIBDB .word 0xFC000000 /* invalid register number,marks end of table*/ _xtensa_reginfo_table_end: +#endif diff --git a/arch/xtensa/kernel/entry.S b/arch/xtensa/kernel/entry.S index 89e409e..c0b56b1 100644 --- a/arch/xtensa/kernel/entry.S +++ b/arch/xtensa/kernel/entry.S @@ -24,7 +24,7 @@ #include <asm/pgtable.h> #include <asm/page.h> #include <asm/signal.h> -#include <xtensa/coreasm.h> +#include <asm/tlbflush.h> /* Unimplemented features. */ @@ -364,7 +364,7 @@ common_exception: movi a2, 1 extui a3, a3, 0, 1 # a3 = PS.INTLEVEL[0] moveqz a3, a2, a0 # a3 = 1 iff interrupt exception - movi a2, PS_WOE_MASK + movi a2, 1 << PS_WOE_BIT or a3, a3, a2 rsr a0, EXCCAUSE xsr a3, PS @@ -399,7 +399,7 @@ common_exception_return: /* Jump if we are returning from kernel exceptions. */ 1: l32i a3, a1, PT_PS - _bbsi.l a3, PS_UM_SHIFT, 2f + _bbsi.l a3, PS_UM_BIT, 2f j kernel_exception_exit /* Specific to a user exception exit: @@ -422,7 +422,7 @@ common_exception_return: * (Hint: There is only one user exception frame on stack) */ - movi a3, PS_WOE_MASK + movi a3, 1 << PS_WOE_BIT _bbsi.l a4, TIF_NEED_RESCHED, 3f _bbci.l a4, TIF_SIGPENDING, 4f @@ -694,7 +694,7 @@ common_exception_exit: ENTRY(debug_exception) rsr a0, EPS + XCHAL_DEBUGLEVEL - bbsi.l a0, PS_EXCM_SHIFT, 1f # exception mode + bbsi.l a0, PS_EXCM_BIT, 1f # exception mode /* Set EPC_1 and EXCCAUSE */ @@ -707,7 +707,7 @@ ENTRY(debug_exception) /* Restore PS to the value before the debug exc but with PS.EXCM set.*/ - movi a2, 1 << PS_EXCM_SHIFT + movi a2, 1 << PS_EXCM_BIT or a2, a0, a2 movi a0, debug_exception # restore a3, debug jump vector wsr a2, PS @@ -715,7 +715,7 @@ ENTRY(debug_exception) /* Switch to kernel/user stack, restore jump vector, and save a0 */ - bbsi.l a2, PS_UM_SHIFT, 2f # jump if user mode + bbsi.l a2, PS_UM_BIT, 2f # jump if user mode addi a2, a1, -16-PT_SIZE # assume kernel stack s32i a0, a2, PT_AREG0 @@ -778,7 +778,7 @@ ENTRY(unrecoverable_exception) wsr a1, WINDOWBASE rsync - movi a1, PS_WOE_MASK | 1 + movi a1, (1 << PS_WOE_BIT) | 1 wsr a1, PS rsync @@ -1491,7 +1491,7 @@ ENTRY(_spill_registers) */ rsr a0, PS - _bbci.l a0, PS_UM_SHIFT, 1f + _bbci.l a0, PS_UM_BIT, 1f /* User space: Setup a dummy frame and kill application. * Note: We assume EXC_TABLE_KSTK contains a valid stack pointer. @@ -1510,7 +1510,7 @@ ENTRY(_spill_registers) l32i a1, a3, EXC_TABLE_KSTK wsr a3, EXCSAVE_1 - movi a4, PS_WOE_MASK | 1 + movi a4, (1 << PS_WOE_BIT) | 1 wsr a4, PS rsync @@ -1612,7 +1612,7 @@ ENTRY(fast_second_level_miss) rsr a1, PTEVADDR srli a1, a1, PAGE_SHIFT slli a1, a1, PAGE_SHIFT # ptevaddr & PAGE_MASK - addi a1, a1, DTLB_WAY_PGTABLE # ... + way_number + addi a1, a1, DTLB_WAY_PGD # ... + way_number wdtlb a0, a1 dsync @@ -1654,7 +1654,7 @@ ENTRY(fast_second_level_miss) mov a1, a2 rsr a2, PS - bbsi.l a2, PS_UM_SHIFT, 1f + bbsi.l a2, PS_UM_BIT, 1f j _kernel_exception 1: j _user_exception @@ -1753,7 +1753,7 @@ ENTRY(fast_store_prohibited) mov a1, a2 rsr a2, PS - bbsi.l a2, PS_UM_SHIFT, 1f + bbsi.l a2, PS_UM_BIT, 1f j _kernel_exception 1: j _user_exception @@ -1924,7 +1924,7 @@ ENTRY(_switch_to) /* Disable ints while we manipulate the stack pointer; spill regs. */ - movi a5, PS_EXCM_MASK | LOCKLEVEL + movi a5, (1 << PS_EXCM_BIT) | LOCKLEVEL xsr a5, PS rsr a3, EXCSAVE_1 rsync diff --git a/arch/xtensa/kernel/head.S b/arch/xtensa/kernel/head.S index c07cb25..ea89910 100644 --- a/arch/xtensa/kernel/head.S +++ b/arch/xtensa/kernel/head.S @@ -15,9 +15,9 @@ * Kevin Chea */ -#include <xtensa/cacheasm.h> #include <asm/processor.h> #include <asm/page.h> +#include <asm/cacheasm.h> /* * This module contains the entry code for kernel images. It performs the @@ -32,13 +32,6 @@ * */ - .macro iterate from, to , cmd - .ifeq ((\to - \from) & ~0xfff) - \cmd \from - iterate "(\from+1)", \to, \cmd - .endif - .endm - /* * _start * @@ -64,7 +57,7 @@ _startup: /* Disable interrupts and exceptions. */ - movi a0, XCHAL_PS_EXCM_MASK + movi a0, LOCKLEVEL wsr a0, PS /* Preserve the pointer to the boot parameter list in EXCSAVE_1 */ @@ -91,11 +84,11 @@ _startup: movi a1, 15 wsr a0, ICOUNTLEVEL - .macro reset_dbreak num - wsr a0, DBREAKC + \num - .endm - - iterate 0, XCHAL_NUM_IBREAK-1, reset_dbreak + .set _index, 0 + .rept XCHAL_NUM_DBREAK - 1 + wsr a0, DBREAKC + _index + .set _index, _index + 1 + .endr #endif /* Clear CCOUNT (not really necessary, but nice) */ @@ -110,10 +103,11 @@ _startup: /* Disable all timers. */ - .macro reset_timer num - wsr a0, CCOMPARE_0 + \num - .endm - iterate 0, XCHAL_NUM_TIMERS-1, reset_timer + .set _index, 0 + .rept XCHAL_NUM_TIMERS - 1 + wsr a0, CCOMPARE + _index + .set _index, _index + 1 + .endr /* Interrupt initialization. */ @@ -139,12 +133,21 @@ _startup: rsync /* Initialize the caches. - * Does not include flushing writeback d-cache. - * a6, a7 are just working registers (clobbered). + * a2, a3 are just working registers (clobbered). */ - icache_reset a2, a3 - dcache_reset a2, a3 +#if XCHAL_DCACHE_LINE_LOCKABLE + ___unlock_dcache_all a2 a3 +#endif + +#if XCHAL_ICACHE_LINE_LOCKABLE + ___unlock_icache_all a2 a3 +#endif + + ___invalidate_dcache_all a2 a3 + ___invalidate_icache_all a2 a3 + + isync /* Unpack data sections * @@ -181,9 +184,9 @@ _startup: movi a2, _bss_start # start of BSS movi a3, _bss_end # end of BSS -1: addi a2, a2, 4 + __loopt a2, a3, a4, 2 s32i a0, a2, 0 - blt a2, a3, 1b + __endla a2, a4, 4 #if XCHAL_DCACHE_IS_WRITEBACK @@ -191,7 +194,7 @@ _startup: * instructions/data are available. */ - dcache_writeback_all a2, a3 + ___flush_dcache_all a2 a3 #endif /* Setup stack and enable window exceptions (keep irqs disabled) */ diff --git a/arch/xtensa/kernel/pci-dma.c b/arch/xtensa/kernel/pci-dma.c index 6648fa9..ca76f07 100644 --- a/arch/xtensa/kernel/pci-dma.c +++ b/arch/xtensa/kernel/pci-dma.c @@ -1,5 +1,5 @@ /* - * arch/xtensa/kernel/pci-dma.c + * arch/xtensa/pci-dma.c * * DMA coherent memory allocation. * @@ -29,28 +29,48 @@ */ void * -dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp) +dma_alloc_coherent(struct device *dev,size_t size,dma_addr_t *handle,gfp_t flag) { - void *ret; + unsigned long ret; + unsigned long uncached = 0; /* ignore region speicifiers */ - gfp &= ~(__GFP_DMA | __GFP_HIGHMEM); - if (dev == NULL || (*dev->dma_mask < 0xffffffff)) - gfp |= GFP_DMA; - ret = (void *)__get_free_pages(gfp, get_order(size)); + flag &= ~(__GFP_DMA | __GFP_HIGHMEM); - if (ret != NULL) { - memset(ret, 0, size); - *handle = virt_to_bus(ret); + if (dev == NULL || (dev->coherent_dma_mask < 0xffffffff)) + flag |= GFP_DMA; + ret = (unsigned long)__get_free_pages(flag, get_order(size)); + + if (ret == 0) + return NULL; + + /* We currently don't support coherent memory outside KSEG */ + + if (ret < XCHAL_KSEG_CACHED_VADDR + || ret >= XCHAL_KSEG_CACHED_VADDR + XCHAL_KSEG_SIZE) + BUG(); + + + if (ret != 0) { + memset((void*) ret, 0, size); + uncached = ret+XCHAL_KSEG_BYPASS_VADDR-XCHAL_KSEG_CACHED_VADDR; + *handle = virt_to_bus((void*)ret); + __flush_invalidate_dcache_range(ret, size); } - return (void*) BYPASS_ADDR((unsigned long)ret); + + return (void*)uncached; } void dma_free_coherent(struct device *hwdev, size_t size, void *vaddr, dma_addr_t dma_handle) { - free_pages(CACHED_ADDR((unsigned long)vaddr), get_order(size)); + long addr=(long)vaddr+XCHAL_KSEG_CACHED_VADDR-XCHAL_KSEG_BYPASS_VADDR; + + if (addr < 0 || addr >= XCHAL_KSEG_SIZE) + BUG(); + + free_pages(addr, get_order(size)); } diff --git a/arch/xtensa/kernel/process.c b/arch/xtensa/kernel/process.c index a7c4178..3785f34 100644 --- a/arch/xtensa/kernel/process.c +++ b/arch/xtensa/kernel/process.c @@ -1,4 +1,3 @@ -// TODO verify coprocessor handling /* * arch/xtensa/kernel/process.c * @@ -43,7 +42,7 @@ #include <asm/irq.h> #include <asm/atomic.h> #include <asm/asm-offsets.h> -#include <asm/coprocessor.h> +#include <asm/regs.h> extern void ret_from_fork(void); @@ -67,25 +66,6 @@ void (*pm_power_off)(void) = NULL; EXPORT_SYMBOL(pm_power_off); -#if XCHAL_CP_NUM > 0 - -/* - * Coprocessor ownership. - */ - -coprocessor_info_t coprocessor_info[] = { - { 0, XTENSA_CPE_CP0_OFFSET }, - { 0, XTENSA_CPE_CP1_OFFSET }, - { 0, XTENSA_CPE_CP2_OFFSET }, - { 0, XTENSA_CPE_CP3_OFFSET }, - { 0, XTENSA_CPE_CP4_OFFSET }, - { 0, XTENSA_CPE_CP5_OFFSET }, - { 0, XTENSA_CPE_CP6_OFFSET }, - { 0, XTENSA_CPE_CP7_OFFSET }, -}; - -#endif - /* * Powermanagement idle function, if any is provided by the platform. */ @@ -110,12 +90,10 @@ void cpu_idle(void) void exit_thread(void) { - release_coprocessors(current); /* Empty macro if no CPs are defined */ } void flush_thread(void) { - release_coprocessors(current); /* Empty macro if no CPs are defined */ } /* @@ -275,7 +253,7 @@ void do_copy_regs (xtensa_gregset_t *elfregs, struct pt_regs *regs, */ elfregs->pc = regs->pc; - elfregs->ps = (regs->ps & ~XCHAL_PS_EXCM_MASK); + elfregs->ps = (regs->ps & ~(1 << PS_EXCM_BIT)); elfregs->exccause = regs->exccause; elfregs->excvaddr = regs->excvaddr; elfregs->windowbase = regs->windowbase; @@ -325,7 +303,7 @@ void do_restore_regs (xtensa_gregset_t *elfregs, struct pt_regs *regs, */ regs->pc = elfregs->pc; - regs->ps = (elfregs->ps | XCHAL_PS_EXCM_MASK); + regs->ps = (elfregs->ps | (1 << PS_EXCM_BIT)); regs->exccause = elfregs->exccause; regs->excvaddr = elfregs->excvaddr; regs->windowbase = elfregs->windowbase; @@ -459,16 +437,7 @@ int do_restore_fpregs (elf_fpregset_t *fpregs, struct pt_regs *regs, int dump_task_fpu(struct pt_regs *regs, struct task_struct *task, elf_fpregset_t *r) { -/* see asm/coprocessor.h for this magic number 16 */ -#if XTENSA_CP_EXTRA_SIZE > 16 - do_save_fpregs (r, regs, task); - - /* For now, bit 16 means some extra state may be present: */ -// FIXME!! need to track to return more accurate mask - return 0x10000 | XCHAL_CP_MASK; -#else return 0; /* no coprocessors active on this processor */ -#endif } /* diff --git a/arch/xtensa/kernel/ptrace.c b/arch/xtensa/kernel/ptrace.c index 9aea23c..604c3c3 100644 --- a/arch/xtensa/kernel/ptrace.c +++ b/arch/xtensa/kernel/ptrace.c @@ -96,7 +96,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) /* Note: PS.EXCM is not set while user task is running; * its being set in regs is for exception handling * convenience. */ - tmp = (regs->ps & ~XCHAL_PS_EXCM_MASK); + tmp = (regs->ps & ~(1 << PS_EXCM_BIT)); break; case REG_WB: tmp = regs->windowbase; diff --git a/arch/xtensa/kernel/setup.c b/arch/xtensa/kernel/setup.c index c99ab72..b6374c0 100644 --- a/arch/xtensa/kernel/setup.c +++ b/arch/xtensa/kernel/setup.c @@ -42,8 +42,6 @@ #include <asm/page.h> #include <asm/setup.h> -#include <xtensa/config/system.h> - #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE) struct screen_info screen_info = { 0, 24, 0, 0, 0, 80, 0, 0, 0, 24, 1, 16}; #endif @@ -336,7 +334,7 @@ c_show(struct seq_file *f, void *slot) /* high-level stuff */ seq_printf(f,"processor\t: 0\n" "vendor_id\t: Tensilica\n" - "model\t\t: Xtensa " XCHAL_HW_RELEASE_NAME "\n" + "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n" "core ID\t\t: " XCHAL_CORE_ID "\n" "build ID\t: 0x%x\n" "byte order\t: %s\n" @@ -420,25 +418,6 @@ c_show(struct seq_file *f, void *slot) XCHAL_NUM_TIMERS, XCHAL_DEBUGLEVEL); - /* Coprocessors */ -#if XCHAL_HAVE_CP - seq_printf(f, "coprocessors\t: %d\n", XCHAL_CP_NUM); -#else - seq_printf(f, "coprocessors\t: none\n"); -#endif - - /* {I,D}{RAM,ROM} and XLMI */ - seq_printf(f,"inst ROMs\t: %d\n" - "inst RAMs\t: %d\n" - "data ROMs\t: %d\n" - "data RAMs\t: %d\n" - "XLMI ports\t: %d\n", - XCHAL_NUM_IROM, - XCHAL_NUM_IRAM, - XCHAL_NUM_DROM, - XCHAL_NUM_DRAM, - XCHAL_NUM_XLMI); - /* Cache */ seq_printf(f,"icache line size: %d\n" "icache ways\t: %d\n" @@ -466,24 +445,6 @@ c_show(struct seq_file *f, void *slot) XCHAL_DCACHE_WAYS, XCHAL_DCACHE_SIZE); - /* MMU */ - seq_printf(f,"ASID bits\t: %d\n" - "ASID invalid\t: %d\n" - "ASID kernel\t: %d\n" - "rings\t\t: %d\n" - "itlb ways\t: %d\n" - "itlb AR ways\t: %d\n" - "dtlb ways\t: %d\n" - "dtlb AR ways\t: %d\n", - XCHAL_MMU_ASID_BITS, - XCHAL_MMU_ASID_INVALID, - XCHAL_MMU_ASID_KERNEL, - XCHAL_MMU_RINGS, - XCHAL_ITLB_WAYS, - XCHAL_ITLB_ARF_WAYS, - XCHAL_DTLB_WAYS, - XCHAL_DTLB_ARF_WAYS); - return 0; } diff --git a/arch/xtensa/kernel/signal.c b/arch/xtensa/kernel/signal.c index c494f08..6af7f41 100644 --- a/arch/xtensa/kernel/signal.c +++ b/arch/xtensa/kernel/signal.c @@ -12,8 +12,8 @@ * */ -#include <xtensa/config/core.h> -#include <xtensa/hal.h> +#include <asm/variant/core.h> +#include <asm/coprocessor.h> #include <linux/sched.h> #include <linux/mm.h> #include <linux/smp.h> @@ -216,8 +216,8 @@ restore_sigcontext(struct pt_regs *regs, struct sigcontext *sc) * handler, or the user mode value doesn't matter (e.g. PS.OWB). */ err |= __get_user(ps, &sc->sc_ps); - regs->ps = (regs->ps & ~XCHAL_PS_CALLINC_MASK) - | (ps & XCHAL_PS_CALLINC_MASK); + regs->ps = (regs->ps & ~PS_CALLINC_MASK) + | (ps & PS_CALLINC_MASK); /* Additional corruption checks */ @@ -280,7 +280,7 @@ flush_my_cpstate(struct task_struct *tsk) static int save_cpextra (struct _cpstate *buf) { -#if (XCHAL_EXTRA_SA_SIZE == 0) && (XCHAL_CP_NUM == 0) +#if XCHAL_CP_NUM == 0 return 0; #else @@ -497,8 +497,10 @@ gen_return_code(unsigned char *codemem, unsigned int use_rt_sigreturn) /* Flush generated code out of the data cache */ - if (err == 0) - __flush_invalidate_cache_range((unsigned long)codemem, 6UL); + if (err == 0) { + __invalidate_icache_range((unsigned long)codemem, 6UL); + __flush_invalidate_dcache_range((unsigned long)codemem, 6UL); + } return err; } diff --git a/arch/xtensa/kernel/syscalls.c b/arch/xtensa/kernel/syscalls.c index f49cb23..f9a5a75 100644 --- a/arch/xtensa/kernel/syscalls.c +++ b/arch/xtensa/kernel/syscalls.c @@ -175,8 +175,8 @@ void system_call (struct pt_regs *regs) * interrupts in the first place: */ local_save_flags (ps); - local_irq_restore((ps & ~XCHAL_PS_INTLEVEL_MASK) | - (regs->ps & XCHAL_PS_INTLEVEL_MASK) ); + local_irq_restore((ps & ~PS_INTLEVEL_MASK) | + (regs->ps & PS_INTLEVEL_MASK) ); if (syscallnr > __NR_Linux_syscalls) { regs->areg[2] = -ENOSYS; diff --git a/arch/xtensa/kernel/traps.c b/arch/xtensa/kernel/traps.c index ce077d6..693ab26 100644 --- a/arch/xtensa/kernel/traps.c +++ b/arch/xtensa/kernel/traps.c @@ -75,7 +75,7 @@ extern void system_call (struct pt_regs*); #define USER 0x02 #define COPROCESSOR(x) \ -{ XCHAL_EXCCAUSE_COPROCESSOR ## x ## _DISABLED, USER, fast_coprocessor } +{ EXCCAUSE_COPROCESSOR ## x ## _DISABLED, USER, fast_coprocessor } typedef struct { int cause; @@ -85,38 +85,38 @@ typedef struct { dispatch_init_table_t __init dispatch_init_table[] = { -{ XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION, 0, do_illegal_instruction}, -{ XCHAL_EXCCAUSE_SYSTEM_CALL, KRNL, fast_syscall_kernel }, -{ XCHAL_EXCCAUSE_SYSTEM_CALL, USER, fast_syscall_user }, -{ XCHAL_EXCCAUSE_SYSTEM_CALL, 0, system_call }, -/* XCHAL_EXCCAUSE_INSTRUCTION_FETCH unhandled */ -/* XCHAL_EXCCAUSE_LOAD_STORE_ERROR unhandled*/ -{ XCHAL_EXCCAUSE_LEVEL1_INTERRUPT, 0, do_interrupt }, -{ XCHAL_EXCCAUSE_ALLOCA, USER|KRNL, fast_alloca }, -/* XCHAL_EXCCAUSE_INTEGER_DIVIDE_BY_ZERO unhandled */ -/* XCHAL_EXCCAUSE_PRIVILEGED unhandled */ +{ EXCCAUSE_ILLEGAL_INSTRUCTION, 0, do_illegal_instruction}, +{ EXCCAUSE_SYSTEM_CALL, KRNL, fast_syscall_kernel }, +{ EXCCAUSE_SYSTEM_CALL, USER, fast_syscall_user }, +{ EXCCAUSE_SYSTEM_CALL, 0, system_call }, +/* EXCCAUSE_INSTRUCTION_FETCH unhandled */ +/* EXCCAUSE_LOAD_STORE_ERROR unhandled*/ +{ EXCCAUSE_LEVEL1_INTERRUPT, 0, do_interrupt }, +{ EXCCAUSE_ALLOCA, USER|KRNL, fast_alloca }, +/* EXCCAUSE_INTEGER_DIVIDE_BY_ZERO unhandled */ +/* EXCCAUSE_PRIVILEGED unhandled */ #if XCHAL_UNALIGNED_LOAD_EXCEPTION || XCHAL_UNALIGNED_STORE_EXCEPTION #ifdef CONFIG_UNALIGNED_USER -{ XCHAL_EXCCAUSE_UNALIGNED, USER, fast_unaligned }, +{ EXCCAUSE_UNALIGNED, USER, fast_unaligned }, #else -{ XCHAL_EXCCAUSE_UNALIGNED, 0, do_unaligned_user }, +{ EXCCAUSE_UNALIGNED, 0, do_unaligned_user }, #endif -{ XCHAL_EXCCAUSE_UNALIGNED, KRNL, fast_unaligned }, +{ EXCCAUSE_UNALIGNED, KRNL, fast_unaligned }, #endif -{ XCHAL_EXCCAUSE_ITLB_MISS, 0, do_page_fault }, -{ XCHAL_EXCCAUSE_ITLB_MISS, USER|KRNL, fast_second_level_miss}, -{ XCHAL_EXCCAUSE_ITLB_MULTIHIT, 0, do_multihit }, -{ XCHAL_EXCCAUSE_ITLB_PRIVILEGE, 0, do_page_fault }, -/* XCHAL_EXCCAUSE_SIZE_RESTRICTION unhandled */ -{ XCHAL_EXCCAUSE_FETCH_CACHE_ATTRIBUTE, 0, do_page_fault }, -{ XCHAL_EXCCAUSE_DTLB_MISS, USER|KRNL, fast_second_level_miss}, -{ XCHAL_EXCCAUSE_DTLB_MISS, 0, do_page_fault }, -{ XCHAL_EXCCAUSE_DTLB_MULTIHIT, 0, do_multihit }, -{ XCHAL_EXCCAUSE_DTLB_PRIVILEGE, 0, do_page_fault }, -/* XCHAL_EXCCAUSE_DTLB_SIZE_RESTRICTION unhandled */ -{ XCHAL_EXCCAUSE_STORE_CACHE_ATTRIBUTE, USER|KRNL, fast_store_prohibited }, -{ XCHAL_EXCCAUSE_STORE_CACHE_ATTRIBUTE, 0, do_page_fault }, -{ XCHAL_EXCCAUSE_LOAD_CACHE_ATTRIBUTE, 0, do_page_fault }, +{ EXCCAUSE_ITLB_MISS, 0, do_page_fault }, +{ EXCCAUSE_ITLB_MISS, USER|KRNL, fast_second_level_miss}, +{ EXCCAUSE_ITLB_MULTIHIT, 0, do_multihit }, +{ EXCCAUSE_ITLB_PRIVILEGE, 0, do_page_fault }, +/* EXCCAUSE_SIZE_RESTRICTION unhandled */ +{ EXCCAUSE_FETCH_CACHE_ATTRIBUTE, 0, do_page_fault }, +{ EXCCAUSE_DTLB_MISS, USER|KRNL, fast_second_level_miss}, +{ EXCCAUSE_DTLB_MISS, 0, do_page_fault }, +{ EXCCAUSE_DTLB_MULTIHIT, 0, do_multihit }, +{ EXCCAUSE_DTLB_PRIVILEGE, 0, do_page_fault }, +/* EXCCAUSE_DTLB_SIZE_RESTRICTION unhandled */ +{ EXCCAUSE_STORE_CACHE_ATTRIBUTE, USER|KRNL, fast_store_prohibited }, +{ EXCCAUSE_STORE_CACHE_ATTRIBUTE, 0, do_page_fault }, +{ EXCCAUSE_LOAD_CACHE_ATTRIBUTE, 0, do_page_fault }, /* XCCHAL_EXCCAUSE_FLOATING_POINT unhandled */ #if (XCHAL_CP_MASK & 1) COPROCESSOR(0), diff --git a/arch/xtensa/kernel/vectors.S b/arch/xtensa/kernel/vectors.S index 0e74397..eb2d7bb 100644 --- a/arch/xtensa/kernel/vectors.S +++ b/arch/xtensa/kernel/vectors.S @@ -53,6 +53,8 @@ #include <asm/thread_info.h> #include <asm/processor.h> +#define WINDOW_VECTORS_SIZE 0x180 + /* * User exception vector. (Exceptions with PS.UM == 1, PS.EXCM == 0) @@ -210,7 +212,7 @@ ENTRY(_DoubleExceptionVector) /* Check for kernel double exception (usually fatal). */ rsr a3, PS - _bbci.l a3, PS_UM_SHIFT, .Lksp + _bbci.l a3, PS_UM_BIT, .Lksp /* Check if we are currently handling a window exception. */ /* Note: We don't need to indicate that we enter a critical section. */ @@ -219,7 +221,7 @@ ENTRY(_DoubleExceptionVector) movi a3, XCHAL_WINDOW_VECTORS_VADDR _bltu a0, a3, .Lfixup - addi a3, a3, XSHAL_WINDOW_VECTORS_SIZE + addi a3, a3, WINDOW_VECTORS_SIZE _bgeu a0, a3, .Lfixup /* Window overflow/underflow exception. Get stack pointer. */ @@ -245,7 +247,7 @@ ENTRY(_DoubleExceptionVector) wsr a2, DEPC # save stack pointer temporarily rsr a0, PS - extui a0, a0, XCHAL_PS_OWB_SHIFT, XCHAL_PS_OWB_BITS + extui a0, a0, PS_OWB_SHIFT, 4 wsr a0, WINDOWBASE rsync @@ -312,8 +314,8 @@ ENTRY(_DoubleExceptionVector) .Lksp: /* a0: a0, a1: a1, a2: a2, a3: trashed, depc: depc, excsave: a3 */ rsr a3, EXCCAUSE - beqi a3, XCHAL_EXCCAUSE_ITLB_MISS, 1f - addi a3, a3, -XCHAL_EXCCAUSE_DTLB_MISS + beqi a3, EXCCAUSE_ITLB_MISS, 1f + addi a3, a3, -EXCCAUSE_DTLB_MISS bnez a3, .Lunrecoverable 1: movi a3, fast_second_level_miss_double_kernel jx a3 diff --git a/arch/xtensa/kernel/vmlinux.lds.S b/arch/xtensa/kernel/vmlinux.lds.S index e01131f..a36c104 100644 --- a/arch/xtensa/kernel/vmlinux.lds.S +++ b/arch/xtensa/kernel/vmlinux.lds.S @@ -16,20 +16,17 @@ #include <asm-generic/vmlinux.lds.h> -#define _NOCLANGUAGE -#undef __ASSEMBLER__ -#include <xtensa/config/core.h> -#include <xtensa/config/system.h> +#include <asm/variant/core.h> OUTPUT_ARCH(xtensa) ENTRY(_start) -#if XCHAL_MEMORY_ORDER == XTHAL_BIGENDIAN +#ifdef __XTENSA_EB__ jiffies = jiffies_64 + 4; #else jiffies = jiffies_64; #endif -#define KERNELOFFSET 0x1000 +#define KERNELOFFSET 0xd0001000 /* Note: In the following macros, it would be nice to specify only the vector name and section kind and construct "sym" and "section" using @@ -76,7 +73,7 @@ jiffies = jiffies_64; SECTIONS { - . = XCHAL_KSEG_CACHED_VADDR + KERNELOFFSET; + . = KERNELOFFSET; /* .text section */ _text = .; @@ -160,7 +157,7 @@ SECTIONS /* Initialization code and data: */ - . = ALIGN(1<<XCHAL_MMU_MIN_PTE_PAGE_SIZE); + . = ALIGN(1 << 12); __init_begin = .; .init.text : { _sinittext = .; @@ -224,32 +221,32 @@ SECTIONS .dummy) SECTION_VECTOR (_DebugInterruptVector_literal, .DebugInterruptVector.literal, - XCHAL_INTLEVEL_VECTOR_VADDR(XCHAL_DEBUGLEVEL) - 4, + XCHAL_DEBUG_VECTOR_VADDR - 4, SIZEOF(.WindowVectors.text), .WindowVectors.text) SECTION_VECTOR (_DebugInterruptVector_text, .DebugInterruptVector.text, - XCHAL_INTLEVEL_VECTOR_VADDR(XCHAL_DEBUGLEVEL), + XCHAL_DEBUG_VECTOR_VADDR, 4, .DebugInterruptVector.literal) SECTION_VECTOR (_KernelExceptionVector_literal, .KernelExceptionVector.literal, - XCHAL_KERNELEXC_VECTOR_VADDR - 4, + XCHAL_KERNEL_VECTOR_VADDR - 4, SIZEOF(.DebugInterruptVector.text), .DebugInterruptVector.text) SECTION_VECTOR (_KernelExceptionVector_text, .KernelExceptionVector.text, - XCHAL_KERNELEXC_VECTOR_VADDR, + XCHAL_KERNEL_VECTOR_VADDR, 4, .KernelExceptionVector.literal) SECTION_VECTOR (_UserExceptionVector_literal, .UserExceptionVector.literal, - XCHAL_USEREXC_VECTOR_VADDR - 4, + XCHAL_USER_VECTOR_VADDR - 4, SIZEOF(.KernelExceptionVector.text), .KernelExceptionVector.text) SECTION_VECTOR (_UserExceptionVector_text, .UserExceptionVector.text, - XCHAL_USEREXC_VECTOR_VADDR, + XCHAL_USER_VECTOR_VADDR, 4, .UserExceptionVector.literal) SECTION_VECTOR (_DoubleExceptionVector_literal, @@ -264,7 +261,7 @@ SECTIONS .DoubleExceptionVector.literal) . = (LOADADDR( .DoubleExceptionVector.text ) + SIZEOF( .DoubleExceptionVector.text ) + 3) & ~ 3; - . = ALIGN(1<<XCHAL_MMU_MIN_PTE_PAGE_SIZE); + . = ALIGN(1 << 12); __init_end = .; diff --git a/arch/xtensa/lib/checksum.S b/arch/xtensa/lib/checksum.S index e2d64df..9d9cd99 100644 --- a/arch/xtensa/lib/checksum.S +++ b/arch/xtensa/lib/checksum.S @@ -16,8 +16,7 @@ #include <asm/errno.h> #include <linux/linkage.h> -#define _ASMLANGUAGE -#include <xtensa/config/core.h> +#include <asm/variant/core.h> /* * computes a partial checksum, e.g. for TCP/UDP fragments diff --git a/arch/xtensa/lib/memcopy.S b/arch/xtensa/lib/memcopy.S index e8f6d7e..ddda8f4 100644 --- a/arch/xtensa/lib/memcopy.S +++ b/arch/xtensa/lib/memcopy.S @@ -9,7 +9,7 @@ * Copyright (C) 2002 - 2005 Tensilica Inc. */ -#include <xtensa/coreasm.h> +#include <asm/variant/core.h> .macro src_b r, w0, w1 #ifdef __XTENSA_EB__ diff --git a/arch/xtensa/lib/memset.S b/arch/xtensa/lib/memset.S index 4de2513..56a1749 100644 --- a/arch/xtensa/lib/memset.S +++ b/arch/xtensa/lib/memset.S @@ -11,7 +11,7 @@ * Copyright (C) 2002 Tensilica Inc. */ -#include <xtensa/coreasm.h> +#include <asm/variant/core.h> /* * void *memset(void *dst, int c, size_t length) diff --git a/arch/xtensa/lib/strncpy_user.S b/arch/xtensa/lib/strncpy_user.S index 71d55df..a834057 100644 --- a/arch/xtensa/lib/strncpy_user.S +++ b/arch/xtensa/lib/strncpy_user.S @@ -11,7 +11,7 @@ * Copyright (C) 2002 Tensilica Inc. */ -#include <xtensa/coreasm.h> +#include <asm/variant/core.h> #include <linux/errno.h> /* Load or store instructions that may cause exceptions use the EX macro. */ diff --git a/arch/xtensa/lib/strnlen_user.S b/arch/xtensa/lib/strnlen_user.S index cdff4d6..5e9c1e7 100644 --- a/arch/xtensa/lib/strnlen_user.S +++ b/arch/xtensa/lib/strnlen_user.S @@ -11,7 +11,7 @@ * Copyright (C) 2002 Tensilica Inc. */ -#include <xtensa/coreasm.h> +#include <asm/variant/core.h> /* Load or store instructions that may cause exceptions use the EX macro. */ diff --git a/arch/xtensa/lib/usercopy.S b/arch/xtensa/lib/usercopy.S index 4641ef5..a8ab1d4 100644 --- a/arch/xtensa/lib/usercopy.S +++ b/arch/xtensa/lib/usercopy.S @@ -53,7 +53,7 @@ * a11/ original length */ -#include <xtensa/coreasm.h> +#include <asm/variant/core.h> #ifdef __XTENSA_EB__ #define ALIGN(R, W0, W1) src R, W0, W1 diff --git a/arch/xtensa/mm/fault.c b/arch/xtensa/mm/fault.c index dd0dbec..3dc6f2f 100644 --- a/arch/xtensa/mm/fault.c +++ b/arch/xtensa/mm/fault.c @@ -21,7 +21,7 @@ #include <asm/system.h> #include <asm/pgalloc.h> -unsigned long asid_cache = ASID_FIRST_VERSION; +unsigned long asid_cache = ASID_USER_FIRST; void bad_page_fault(struct pt_regs*, unsigned long, int); /* @@ -58,10 +58,10 @@ void do_page_fault(struct pt_regs *regs) return; } - is_write = (exccause == XCHAL_EXCCAUSE_STORE_CACHE_ATTRIBUTE) ? 1 : 0; - is_exec = (exccause == XCHAL_EXCCAUSE_ITLB_PRIVILEGE || - exccause == XCHAL_EXCCAUSE_ITLB_MISS || - exccause == XCHAL_EXCCAUSE_FETCH_CACHE_ATTRIBUTE) ? 1 : 0; + is_write = (exccause == EXCCAUSE_STORE_CACHE_ATTRIBUTE) ? 1 : 0; + is_exec = (exccause == EXCCAUSE_ITLB_PRIVILEGE || + exccause == EXCCAUSE_ITLB_MISS || + exccause == EXCCAUSE_FETCH_CACHE_ATTRIBUTE) ? 1 : 0; #if 0 printk("[%s:%d:%08x:%d:%08x:%s%s]\n", current->comm, current->pid, diff --git a/arch/xtensa/mm/init.c b/arch/xtensa/mm/init.c index 660ef05..e1ec2d1 100644 --- a/arch/xtensa/mm/init.c +++ b/arch/xtensa/mm/init.c @@ -141,8 +141,8 @@ void __init bootmem_init(void) if (min_low_pfn > max_pfn) panic("No memory found!\n"); - max_low_pfn = max_pfn < MAX_LOW_MEMORY >> PAGE_SHIFT ? - max_pfn : MAX_LOW_MEMORY >> PAGE_SHIFT; + max_low_pfn = max_pfn < MAX_MEM_PFN >> PAGE_SHIFT ? + max_pfn : MAX_MEM_PFN >> PAGE_SHIFT; /* Find an area to use for the bootmem bitmap. */ @@ -215,7 +215,7 @@ void __init init_mmu (void) /* Set rasid register to a known value. */ - set_rasid_register (ASID_ALL_RESERVED); + set_rasid_register (ASID_USER_FIRST); /* Set PTEVADDR special register to the start of the page * table, which is in kernel mappable space (ie. not diff --git a/arch/xtensa/mm/misc.S b/arch/xtensa/mm/misc.S index 327c0f1..ae08533 100644 --- a/arch/xtensa/mm/misc.S +++ b/arch/xtensa/mm/misc.S @@ -19,9 +19,8 @@ #include <linux/linkage.h> #include <asm/page.h> #include <asm/pgtable.h> - -#include <xtensa/cacheasm.h> -#include <xtensa/cacheattrasm.h> +#include <asm/asmmacro.h> +#include <asm/cacheasm.h> /* clear_page (page) */ @@ -74,104 +73,66 @@ ENTRY(copy_page) retw - /* - * void __flush_invalidate_cache_all(void) + * void __invalidate_icache_page(ulong start) */ -ENTRY(__flush_invalidate_cache_all) +ENTRY(__invalidate_icache_page) entry sp, 16 - dcache_writeback_inv_all a2, a3 - icache_invalidate_all a2, a3 - retw -/* - * void __invalidate_icache_all(void) - */ + ___invalidate_icache_page a2 a3 + isync -ENTRY(__invalidate_icache_all) - entry sp, 16 - icache_invalidate_all a2, a3 retw /* - * void __flush_invalidate_dcache_all(void) + * void __invalidate_dcache_page(ulong start) */ -ENTRY(__flush_invalidate_dcache_all) +ENTRY(__invalidate_dcache_page) entry sp, 16 - dcache_writeback_inv_all a2, a3 - retw - -/* - * void __flush_invalidate_cache_range(ulong start, ulong size) - */ + ___invalidate_dcache_page a2 a3 + dsync -ENTRY(__flush_invalidate_cache_range) - entry sp, 16 - mov a4, a2 - mov a5, a3 - dcache_writeback_inv_region a4, a5, a6 - icache_invalidate_region a2, a3, a4 retw /* - * void __invalidate_icache_page(ulong start) + * void __flush_invalidate_dcache_page(ulong start) */ -ENTRY(__invalidate_icache_page) +ENTRY(__flush_invalidate_dcache_page) entry sp, 16 - movi a3, PAGE_SIZE - icache_invalidate_region a2, a3, a4 - retw -/* - * void __invalidate_dcache_page(ulong start) - */ + ___flush_invalidate_dcache_page a2 a3 -ENTRY(__invalidate_dcache_page) - entry sp, 16 - movi a3, PAGE_SIZE - dcache_invalidate_region a2, a3, a4 + dsync retw /* - * void __invalidate_icache_range(ulong start, ulong size) + * void __flush_dcache_page(ulong start) */ -ENTRY(__invalidate_icache_range) +ENTRY(__flush_dcache_page) entry sp, 16 - icache_invalidate_region a2, a3, a4 - retw -/* - * void __invalidate_dcache_range(ulong start, ulong size) - */ + ___flush_dcache_page a2 a3 -ENTRY(__invalidate_dcache_range) - entry sp, 16 - dcache_invalidate_region a2, a3, a4 + dsync retw -/* - * void __flush_dcache_page(ulong start) - */ -ENTRY(__flush_dcache_page) - entry sp, 16 - movi a3, PAGE_SIZE - dcache_writeback_region a2, a3, a4 - retw /* - * void __flush_invalidate_dcache_page(ulong start) + * void __invalidate_icache_range(ulong start, ulong size) */ -ENTRY(__flush_invalidate_dcache_page) +ENTRY(__invalidate_icache_range) entry sp, 16 - movi a3, PAGE_SIZE - dcache_writeback_inv_region a2, a3, a4 + + ___invalidate_icache_range a2 a3 a4 + isync + retw /* @@ -180,195 +141,69 @@ ENTRY(__flush_invalidate_dcache_page) ENTRY(__flush_invalidate_dcache_range) entry sp, 16 - dcache_writeback_inv_region a2, a3, a4 - retw -/* - * void __invalidate_dcache_all(void) - */ + ___flush_invalidate_dcache_range a2 a3 a4 + dsync -ENTRY(__invalidate_dcache_all) - entry sp, 16 - dcache_invalidate_all a2, a3 retw /* - * void __flush_invalidate_dcache_page_phys(ulong start) + * void _flush_dcache_range(ulong start, ulong size) */ -ENTRY(__flush_invalidate_dcache_page_phys) +ENTRY(__flush_dcache_range) entry sp, 16 - movi a3, XCHAL_DCACHE_SIZE - movi a4, PAGE_MASK | 1 - addi a2, a2, 1 - -1: addi a3, a3, -XCHAL_DCACHE_LINESIZE - - ldct a6, a3 + ___flush_dcache_range a2 a3 a4 dsync - and a6, a6, a4 - beq a6, a2, 2f - bgeui a3, 2, 1b - retw -2: diwbi a3, 0 - bgeui a3, 2, 1b retw -ENTRY(check_dcache_low0) - entry sp, 16 - - movi a3, XCHAL_DCACHE_SIZE / 4 - movi a4, PAGE_MASK | 1 - addi a2, a2, 1 - -1: addi a3, a3, -XCHAL_DCACHE_LINESIZE - - ldct a6, a3 - dsync - and a6, a6, a4 - beq a6, a2, 2f - bgeui a3, 2, 1b - retw - -2: j 2b - -ENTRY(check_dcache_high0) - entry sp, 16 - - movi a5, XCHAL_DCACHE_SIZE / 4 - movi a3, XCHAL_DCACHE_SIZE / 2 - movi a4, PAGE_MASK | 1 - addi a2, a2, 1 - -1: addi a3, a3, -XCHAL_DCACHE_LINESIZE - addi a5, a5, -XCHAL_DCACHE_LINESIZE - - ldct a6, a3 - dsync - and a6, a6, a4 - beq a6, a2, 2f - bgeui a5, 2, 1b - retw - -2: j 2b +/* + * void _invalidate_dcache_range(ulong start, ulong size) + */ -ENTRY(check_dcache_low1) +ENTRY(__invalidate_dcache_range) entry sp, 16 - movi a5, XCHAL_DCACHE_SIZE / 4 - movi a3, XCHAL_DCACHE_SIZE * 3 / 4 - movi a4, PAGE_MASK | 1 - addi a2, a2, 1 + ___invalidate_dcache_range a2 a3 a4 -1: addi a3, a3, -XCHAL_DCACHE_LINESIZE - addi a5, a5, -XCHAL_DCACHE_LINESIZE - ldct a6, a3 - dsync - and a6, a6, a4 - beq a6, a2, 2f - bgeui a5, 2, 1b retw -2: j 2b +/* + * void _invalidate_icache_all(void) + */ -ENTRY(check_dcache_high1) +ENTRY(__invalidate_icache_all) entry sp, 16 - movi a5, XCHAL_DCACHE_SIZE / 4 - movi a3, XCHAL_DCACHE_SIZE - movi a4, PAGE_MASK | 1 - addi a2, a2, 1 - -1: addi a3, a3, -XCHAL_DCACHE_LINESIZE - addi a5, a5, -XCHAL_DCACHE_LINESIZE + ___invalidate_icache_all a2 a3 + isync - ldct a6, a3 - dsync - and a6, a6, a4 - beq a6, a2, 2f - bgeui a5, 2, 1b retw -2: j 2b - - /* - * void __invalidate_icache_page_phys(ulong start) + * void _flush_invalidate_dcache_all(void) */ -ENTRY(__invalidate_icache_page_phys) +ENTRY(__flush_invalidate_dcache_all) entry sp, 16 - movi a3, XCHAL_ICACHE_SIZE - movi a4, PAGE_MASK | 1 - addi a2, a2, 1 - -1: addi a3, a3, -XCHAL_ICACHE_LINESIZE - - lict a6, a3 - isync - and a6, a6, a4 - beq a6, a2, 2f - bgeui a3, 2, 1b - retw + ___flush_invalidate_dcache_all a2 a3 + dsync -2: iii a3, 0 - bgeui a3, 2, 1b retw +/* + * void _invalidate_dcache_all(void) + */ -#if 0 - - movi a3, XCHAL_DCACHE_WAYS - 1 - movi a4, PAGE_SIZE - -1: mov a5, a2 - add a6, a2, a4 - -2: diwbi a5, 0 - diwbi a5, XCHAL_DCACHE_LINESIZE - diwbi a5, XCHAL_DCACHE_LINESIZE * 2 - diwbi a5, XCHAL_DCACHE_LINESIZE * 3 - - addi a5, a5, XCHAL_DCACHE_LINESIZE * 4 - blt a5, a6, 2b - - addi a3, a3, -1 - addi a2, a2, XCHAL_DCACHE_SIZE / XCHAL_DCACHE_WAYS - bgez a3, 1b - - retw - -ENTRY(__invalidate_icache_page_index) +ENTRY(__invalidate_dcache_all) entry sp, 16 - movi a3, XCHAL_ICACHE_WAYS - 1 - movi a4, PAGE_SIZE - -1: mov a5, a2 - add a6, a2, a4 - -2: iii a5, 0 - iii a5, XCHAL_ICACHE_LINESIZE - iii a5, XCHAL_ICACHE_LINESIZE * 2 - iii a5, XCHAL_ICACHE_LINESIZE * 3 - - addi a5, a5, XCHAL_ICACHE_LINESIZE * 4 - blt a5, a6, 2b - - addi a3, a3, -1 - addi a2, a2, XCHAL_ICACHE_SIZE / XCHAL_ICACHE_WAYS - bgez a3, 2b + ___invalidate_dcache_all a2 a3 + dsync retw -#endif - - - - - - diff --git a/arch/xtensa/mm/tlb.c b/arch/xtensa/mm/tlb.c index 0fefb866..239461d 100644 --- a/arch/xtensa/mm/tlb.c +++ b/arch/xtensa/mm/tlb.c @@ -24,12 +24,12 @@ static inline void __flush_itlb_all (void) { - int way, index; + int w, i; - for (way = 0; way < XCHAL_ITLB_ARF_WAYS; way++) { - for (index = 0; index < ITLB_ENTRIES_PER_ARF_WAY; index++) { - int entry = way + (index << PAGE_SHIFT); - invalidate_itlb_entry_no_isync (entry); + for (w = 0; w < ITLB_ARF_WAYS; w++) { + for (i = 0; i < (1 << XCHAL_ITLB_ARF_ENTRIES_LOG2); i++) { + int e = w + (i << PAGE_SHIFT); + invalidate_itlb_entry_no_isync(e); } } asm volatile ("isync\n"); @@ -37,12 +37,12 @@ static inline void __flush_itlb_all (void) static inline void __flush_dtlb_all (void) { - int way, index; + int w, i; - for (way = 0; way < XCHAL_DTLB_ARF_WAYS; way++) { - for (index = 0; index < DTLB_ENTRIES_PER_ARF_WAY; index++) { - int entry = way + (index << PAGE_SHIFT); - invalidate_dtlb_entry_no_isync (entry); + for (w = 0; w < DTLB_ARF_WAYS; w++) { + for (i = 0; i < (1 << XCHAL_DTLB_ARF_ENTRIES_LOG2); i++) { + int e = w + (i << PAGE_SHIFT); + invalidate_dtlb_entry_no_isync(e); } } asm volatile ("isync\n"); @@ -63,21 +63,25 @@ void flush_tlb_all (void) void flush_tlb_mm(struct mm_struct *mm) { -#if 0 - printk("[tlbmm<%lx>]\n", (unsigned long)mm->context); -#endif - if (mm == current->active_mm) { int flags; local_save_flags(flags); - get_new_mmu_context(mm, asid_cache); - set_rasid_register(ASID_INSERT(mm->context)); + __get_new_mmu_context(mm); + __load_mmu_context(mm); local_irq_restore(flags); } else mm->context = 0; } +#define _ITLB_ENTRIES (ITLB_ARF_WAYS << XCHAL_ITLB_ARF_ENTRIES_LOG2) +#define _DTLB_ENTRIES (DTLB_ARF_WAYS << XCHAL_DTLB_ARF_ENTRIES_LOG2) +#if _ITLB_ENTRIES > _DTLB_ENTRIES +# define _TLB_ENTRIES _ITLB_ENTRIES +#else +# define _TLB_ENTRIES _DTLB_ENTRIES +#endif + void flush_tlb_range (struct vm_area_struct *vma, unsigned long start, unsigned long end) { @@ -93,7 +97,7 @@ void flush_tlb_range (struct vm_area_struct *vma, #endif local_save_flags(flags); - if (end-start + (PAGE_SIZE-1) <= SMALLEST_NTLB_ENTRIES << PAGE_SHIFT) { + if (end-start + (PAGE_SIZE-1) <= _TLB_ENTRIES << PAGE_SHIFT) { int oldpid = get_rasid_register(); set_rasid_register (ASID_INSERT(mm->context)); start &= PAGE_MASK; @@ -111,9 +115,7 @@ void flush_tlb_range (struct vm_area_struct *vma, set_rasid_register(oldpid); } else { - get_new_mmu_context(mm, asid_cache); - if (mm == current->active_mm) - set_rasid_register(ASID_INSERT(mm->context)); + flush_tlb_mm(mm); } local_irq_restore(flags); } @@ -123,10 +125,6 @@ void flush_tlb_page (struct vm_area_struct *vma, unsigned long page) struct mm_struct* mm = vma->vm_mm; unsigned long flags; int oldpid; -#if 0 - printk("[tlbpage<%02lx,%08lx>]\n", - (unsigned long)mm->context, page); -#endif if(mm->context == NO_CONTEXT) return; @@ -142,404 +140,5 @@ void flush_tlb_page (struct vm_area_struct *vma, unsigned long page) set_rasid_register(oldpid); local_irq_restore(flags); - -#if 0 - flush_tlb_all(); - return; -#endif -} - - -#ifdef DEBUG_TLB - -#define USE_ITLB 0 -#define USE_DTLB 1 - -struct way_config_t { - int indicies; - int indicies_log2; - int pgsz_log2; - int arf; -}; - -static struct way_config_t itlb[XCHAL_ITLB_WAYS] = -{ - { XCHAL_ITLB_SET(XCHAL_ITLB_WAY0_SET, ENTRIES), - XCHAL_ITLB_SET(XCHAL_ITLB_WAY0_SET, ENTRIES_LOG2), - XCHAL_ITLB_SET(XCHAL_ITLB_WAY0_SET, PAGESZ_LOG2_MIN), - XCHAL_ITLB_SET(XCHAL_ITLB_WAY0_SET, ARF) - }, - { XCHAL_ITLB_SET(XCHAL_ITLB_WAY1_SET, ENTRIES), - XCHAL_ITLB_SET(XCHAL_ITLB_WAY1_SET, ENTRIES_LOG2), - XCHAL_ITLB_SET(XCHAL_ITLB_WAY1_SET, PAGESZ_LOG2_MIN), - XCHAL_ITLB_SET(XCHAL_ITLB_WAY1_SET, ARF) - }, - { XCHAL_ITLB_SET(XCHAL_ITLB_WAY2_SET, ENTRIES), - XCHAL_ITLB_SET(XCHAL_ITLB_WAY2_SET, ENTRIES_LOG2), - XCHAL_ITLB_SET(XCHAL_ITLB_WAY2_SET, PAGESZ_LOG2_MIN), - XCHAL_ITLB_SET(XCHAL_ITLB_WAY2_SET, ARF) - }, - { XCHAL_ITLB_SET(XCHAL_ITLB_WAY3_SET, ENTRIES), - XCHAL_ITLB_SET(XCHAL_ITLB_WAY3_SET, ENTRIES_LOG2), - XCHAL_ITLB_SET(XCHAL_ITLB_WAY3_SET, PAGESZ_LOG2_MIN), - XCHAL_ITLB_SET(XCHAL_ITLB_WAY3_SET, ARF) - }, - { XCHAL_ITLB_SET(XCHAL_ITLB_WAY4_SET, ENTRIES), - XCHAL_ITLB_SET(XCHAL_ITLB_WAY4_SET, ENTRIES_LOG2), - XCHAL_ITLB_SET(XCHAL_ITLB_WAY4_SET, PAGESZ_LOG2_MIN), - XCHAL_ITLB_SET(XCHAL_ITLB_WAY4_SET, ARF) - }, - { XCHAL_ITLB_SET(XCHAL_ITLB_WAY5_SET, ENTRIES), - XCHAL_ITLB_SET(XCHAL_ITLB_WAY5_SET, ENTRIES_LOG2), - XCHAL_ITLB_SET(XCHAL_ITLB_WAY5_SET, PAGESZ_LOG2_MIN), - XCHAL_ITLB_SET(XCHAL_ITLB_WAY5_SET, ARF) - }, - { XCHAL_ITLB_SET(XCHAL_ITLB_WAY6_SET, ENTRIES), - XCHAL_ITLB_SET(XCHAL_ITLB_WAY6_SET, ENTRIES_LOG2), - XCHAL_ITLB_SET(XCHAL_ITLB_WAY6_SET, PAGESZ_LOG2_MIN), - XCHAL_ITLB_SET(XCHAL_ITLB_WAY6_SET, ARF) - } -}; - -static struct way_config_t dtlb[XCHAL_DTLB_WAYS] = -{ - { XCHAL_DTLB_SET(XCHAL_DTLB_WAY0_SET, ENTRIES), - XCHAL_DTLB_SET(XCHAL_DTLB_WAY0_SET, ENTRIES_LOG2), - XCHAL_DTLB_SET(XCHAL_DTLB_WAY0_SET, PAGESZ_LOG2_MIN), - XCHAL_DTLB_SET(XCHAL_DTLB_WAY0_SET, ARF) - }, - { XCHAL_DTLB_SET(XCHAL_DTLB_WAY1_SET, ENTRIES), - XCHAL_DTLB_SET(XCHAL_DTLB_WAY1_SET, ENTRIES_LOG2), - XCHAL_DTLB_SET(XCHAL_DTLB_WAY1_SET, PAGESZ_LOG2_MIN), - XCHAL_DTLB_SET(XCHAL_DTLB_WAY1_SET, ARF) - }, - { XCHAL_DTLB_SET(XCHAL_DTLB_WAY2_SET, ENTRIES), - XCHAL_DTLB_SET(XCHAL_DTLB_WAY2_SET, ENTRIES_LOG2), - XCHAL_DTLB_SET(XCHAL_DTLB_WAY2_SET, PAGESZ_LOG2_MIN), - XCHAL_DTLB_SET(XCHAL_DTLB_WAY2_SET, ARF) - }, - { XCHAL_DTLB_SET(XCHAL_DTLB_WAY3_SET, ENTRIES), - XCHAL_DTLB_SET(XCHAL_DTLB_WAY3_SET, ENTRIES_LOG2), - XCHAL_DTLB_SET(XCHAL_DTLB_WAY3_SET, PAGESZ_LOG2_MIN), - XCHAL_DTLB_SET(XCHAL_DTLB_WAY3_SET, ARF) - }, - { XCHAL_DTLB_SET(XCHAL_DTLB_WAY4_SET, ENTRIES), - XCHAL_DTLB_SET(XCHAL_DTLB_WAY4_SET, ENTRIES_LOG2), - XCHAL_DTLB_SET(XCHAL_DTLB_WAY4_SET, PAGESZ_LOG2_MIN), - XCHAL_DTLB_SET(XCHAL_DTLB_WAY4_SET, ARF) - }, - { XCHAL_DTLB_SET(XCHAL_DTLB_WAY5_SET, ENTRIES), - XCHAL_DTLB_SET(XCHAL_DTLB_WAY5_SET, ENTRIES_LOG2), - XCHAL_DTLB_SET(XCHAL_DTLB_WAY5_SET, PAGESZ_LOG2_MIN), - XCHAL_DTLB_SET(XCHAL_DTLB_WAY5_SET, ARF) - }, - { XCHAL_DTLB_SET(XCHAL_DTLB_WAY6_SET, ENTRIES), - XCHAL_DTLB_SET(XCHAL_DTLB_WAY6_SET, ENTRIES_LOG2), - XCHAL_DTLB_SET(XCHAL_DTLB_WAY6_SET, PAGESZ_LOG2_MIN), - XCHAL_DTLB_SET(XCHAL_DTLB_WAY6_SET, ARF) - }, - { XCHAL_DTLB_SET(XCHAL_DTLB_WAY7_SET, ENTRIES), - XCHAL_DTLB_SET(XCHAL_DTLB_WAY7_SET, ENTRIES_LOG2), - XCHAL_DTLB_SET(XCHAL_DTLB_WAY7_SET, PAGESZ_LOG2_MIN), - XCHAL_DTLB_SET(XCHAL_DTLB_WAY7_SET, ARF) - }, - { XCHAL_DTLB_SET(XCHAL_DTLB_WAY8_SET, ENTRIES), - XCHAL_DTLB_SET(XCHAL_DTLB_WAY8_SET, ENTRIES_LOG2), - XCHAL_DTLB_SET(XCHAL_DTLB_WAY8_SET, PAGESZ_LOG2_MIN), - XCHAL_DTLB_SET(XCHAL_DTLB_WAY8_SET, ARF) - }, - { XCHAL_DTLB_SET(XCHAL_DTLB_WAY9_SET, ENTRIES), - XCHAL_DTLB_SET(XCHAL_DTLB_WAY9_SET, ENTRIES_LOG2), - XCHAL_DTLB_SET(XCHAL_DTLB_WAY9_SET, PAGESZ_LOG2_MIN), - XCHAL_DTLB_SET(XCHAL_DTLB_WAY9_SET, ARF) - } -}; - -/* Total number of entries: */ -#define ITLB_TOTAL_ENTRIES \ - XCHAL_ITLB_SET(XCHAL_ITLB_WAY0_SET, ENTRIES) + \ - XCHAL_ITLB_SET(XCHAL_ITLB_WAY1_SET, ENTRIES) + \ - XCHAL_ITLB_SET(XCHAL_ITLB_WAY2_SET, ENTRIES) + \ - XCHAL_ITLB_SET(XCHAL_ITLB_WAY3_SET, ENTRIES) + \ - XCHAL_ITLB_SET(XCHAL_ITLB_WAY4_SET, ENTRIES) + \ - XCHAL_ITLB_SET(XCHAL_ITLB_WAY5_SET, ENTRIES) + \ - XCHAL_ITLB_SET(XCHAL_ITLB_WAY6_SET, ENTRIES) -#define DTLB_TOTAL_ENTRIES \ - XCHAL_DTLB_SET(XCHAL_DTLB_WAY0_SET, ENTRIES) + \ - XCHAL_DTLB_SET(XCHAL_DTLB_WAY1_SET, ENTRIES) + \ - XCHAL_DTLB_SET(XCHAL_DTLB_WAY2_SET, ENTRIES) + \ - XCHAL_DTLB_SET(XCHAL_DTLB_WAY3_SET, ENTRIES) + \ - XCHAL_DTLB_SET(XCHAL_DTLB_WAY4_SET, ENTRIES) + \ - XCHAL_DTLB_SET(XCHAL_DTLB_WAY5_SET, ENTRIES) + \ - XCHAL_DTLB_SET(XCHAL_DTLB_WAY6_SET, ENTRIES) + \ - XCHAL_DTLB_SET(XCHAL_DTLB_WAY7_SET, ENTRIES) + \ - XCHAL_DTLB_SET(XCHAL_DTLB_WAY8_SET, ENTRIES) + \ - XCHAL_DTLB_SET(XCHAL_DTLB_WAY9_SET, ENTRIES) - - -typedef struct { - unsigned va; - unsigned pa; - unsigned char asid; - unsigned char ca; - unsigned char way; - unsigned char index; - unsigned char pgsz_log2; /* 0 .. 32 */ - unsigned char type; /* 0=ITLB 1=DTLB */ -} tlb_dump_entry_t; - -/* Return -1 if a precedes b, +1 if a follows b, 0 if same: */ -int cmp_tlb_dump_info( tlb_dump_entry_t *a, tlb_dump_entry_t *b ) -{ - if (a->asid < b->asid) return -1; - if (a->asid > b->asid) return 1; - if (a->va < b->va) return -1; - if (a->va > b->va) return 1; - if (a->pa < b->pa) return -1; - if (a->pa > b->pa) return 1; - if (a->ca < b->ca) return -1; - if (a->ca > b->ca) return 1; - if (a->way < b->way) return -1; - if (a->way > b->way) return 1; - if (a->index < b->index) return -1; - if (a->index > b->index) return 1; - return 0; -} - -void sort_tlb_dump_info( tlb_dump_entry_t *t, int n ) -{ - int i, j; - /* Simple O(n*n) sort: */ - for (i = 0; i < n-1; i++) - for (j = i+1; j < n; j++) - if (cmp_tlb_dump_info(t+i, t+j) > 0) { - tlb_dump_entry_t tmp = t[i]; - t[i] = t[j]; - t[j] = tmp; - } -} - - -static tlb_dump_entry_t itlb_dump_info[ITLB_TOTAL_ENTRIES]; -static tlb_dump_entry_t dtlb_dump_info[DTLB_TOTAL_ENTRIES]; - - -static inline char *way_type (int type) -{ - return type ? "autorefill" : "non-autorefill"; -} - -void print_entry (struct way_config_t *way_info, - unsigned int way, - unsigned int index, - unsigned int virtual, - unsigned int translation) -{ - char valid_chr; - unsigned int va, pa, asid, ca; - - va = virtual & - ~((1 << (way_info->pgsz_log2 + way_info->indicies_log2)) - 1); - asid = virtual & ((1 << XCHAL_MMU_ASID_BITS) - 1); - pa = translation & ~((1 << way_info->pgsz_log2) - 1); - ca = translation & ((1 << XCHAL_MMU_CA_BITS) - 1); - valid_chr = asid ? 'V' : 'I'; - - /* Compute and incorporate the effect of the index bits on the - * va. It's more useful for kernel debugging, since we always - * want to know the effective va anyway. */ - - va += index << way_info->pgsz_log2; - - printk ("\t[%d,%d] (%c) vpn 0x%.8x ppn 0x%.8x asid 0x%.2x am 0x%x\n", - way, index, valid_chr, va, pa, asid, ca); -} - -void print_itlb_entry (struct way_config_t *way_info, int way, int index) -{ - print_entry (way_info, way, index, - read_itlb_virtual (way + (index << way_info->pgsz_log2)), - read_itlb_translation (way + (index << way_info->pgsz_log2))); -} - -void print_dtlb_entry (struct way_config_t *way_info, int way, int index) -{ - print_entry (way_info, way, index, - read_dtlb_virtual (way + (index << way_info->pgsz_log2)), - read_dtlb_translation (way + (index << way_info->pgsz_log2))); -} - -void dump_itlb (void) -{ - int way, index; - - printk ("\nITLB: ways = %d\n", XCHAL_ITLB_WAYS); - - for (way = 0; way < XCHAL_ITLB_WAYS; way++) { - printk ("\nWay: %d, Entries: %d, MinPageSize: %d, Type: %s\n", - way, itlb[way].indicies, - itlb[way].pgsz_log2, way_type(itlb[way].arf)); - for (index = 0; index < itlb[way].indicies; index++) { - print_itlb_entry(&itlb[way], way, index); - } - } -} - -void dump_dtlb (void) -{ - int way, index; - - printk ("\nDTLB: ways = %d\n", XCHAL_DTLB_WAYS); - - for (way = 0; way < XCHAL_DTLB_WAYS; way++) { - printk ("\nWay: %d, Entries: %d, MinPageSize: %d, Type: %s\n", - way, dtlb[way].indicies, - dtlb[way].pgsz_log2, way_type(dtlb[way].arf)); - for (index = 0; index < dtlb[way].indicies; index++) { - print_dtlb_entry(&dtlb[way], way, index); - } - } -} - -void dump_tlb (tlb_dump_entry_t *tinfo, struct way_config_t *config, - int entries, int ways, int type, int show_invalid) -{ - tlb_dump_entry_t *e = tinfo; - int way, i; - - /* Gather all info: */ - for (way = 0; way < ways; way++) { - struct way_config_t *cfg = config + way; - for (i = 0; i < cfg->indicies; i++) { - unsigned wayindex = way + (i << cfg->pgsz_log2); - unsigned vv = (type ? read_dtlb_virtual (wayindex) - : read_itlb_virtual (wayindex)); - unsigned pp = (type ? read_dtlb_translation (wayindex) - : read_itlb_translation (wayindex)); - - /* Compute and incorporate the effect of the index bits on the - * va. It's more useful for kernel debugging, since we always - * want to know the effective va anyway. */ - - e->va = (vv & ~((1 << (cfg->pgsz_log2 + cfg->indicies_log2)) - 1)); - e->va += (i << cfg->pgsz_log2); - e->pa = (pp & ~((1 << cfg->pgsz_log2) - 1)); - e->asid = (vv & ((1 << XCHAL_MMU_ASID_BITS) - 1)); - e->ca = (pp & ((1 << XCHAL_MMU_CA_BITS) - 1)); - e->way = way; - e->index = i; - e->pgsz_log2 = cfg->pgsz_log2; - e->type = type; - e++; - } - } -#if 1 - /* Sort by ASID and VADDR: */ - sort_tlb_dump_info (tinfo, entries); -#endif - - /* Display all sorted info: */ - printk ("\n%cTLB dump:\n", (type ? 'D' : 'I')); - for (e = tinfo, i = 0; i < entries; i++, e++) { -#if 0 - if (e->asid == 0 && !show_invalid) - continue; -#endif - printk ("%c way=%d i=%d ASID=%02X V=%08X -> P=%08X CA=%X (%d %cB)\n", - (e->type ? 'D' : 'I'), e->way, e->index, - e->asid, e->va, e->pa, e->ca, - (1 << (e->pgsz_log2 % 10)), - " kMG"[e->pgsz_log2 / 10] - ); - } -} - -void dump_tlbs2 (int showinv) -{ - dump_tlb (itlb_dump_info, itlb, ITLB_TOTAL_ENTRIES, XCHAL_ITLB_WAYS, 0, showinv); - dump_tlb (dtlb_dump_info, dtlb, DTLB_TOTAL_ENTRIES, XCHAL_DTLB_WAYS, 1, showinv); -} - -void dump_all_tlbs (void) -{ - dump_tlbs2 (1); -} - -void dump_valid_tlbs (void) -{ - dump_tlbs2 (0); } - -void dump_tlbs (void) -{ - dump_itlb(); - dump_dtlb(); -} - -void dump_cache_tag(int dcache, int idx) -{ - int w, i, s, e; - unsigned long tag, index; - unsigned long num_lines, num_ways, cache_size, line_size; - - num_ways = dcache ? XCHAL_DCACHE_WAYS : XCHAL_ICACHE_WAYS; - cache_size = dcache ? XCHAL_DCACHE_SIZE : XCHAL_ICACHE_SIZE; - line_size = dcache ? XCHAL_DCACHE_LINESIZE : XCHAL_ICACHE_LINESIZE; - - num_lines = cache_size / num_ways; - - s = 0; e = num_lines; - - if (idx >= 0) - e = (s = idx * line_size) + 1; - - for (i = s; i < e; i+= line_size) { - printk("\nline %#08x:", i); - for (w = 0; w < num_ways; w++) { - index = w * num_lines + i; - if (dcache) - __asm__ __volatile__("ldct %0, %1\n\t" - : "=a"(tag) : "a"(index)); - else - __asm__ __volatile__("lict %0, %1\n\t" - : "=a"(tag) : "a"(index)); - - printk(" %#010lx", tag); - } - } - printk ("\n"); -} - -void dump_icache(int index) -{ - unsigned long data, addr; - int w, i; - - const unsigned long num_ways = XCHAL_ICACHE_WAYS; - const unsigned long cache_size = XCHAL_ICACHE_SIZE; - const unsigned long line_size = XCHAL_ICACHE_LINESIZE; - const unsigned long num_lines = cache_size / num_ways / line_size; - - for (w = 0; w < num_ways; w++) { - printk ("\nWay %d", w); - - for (i = 0; i < line_size; i+= 4) { - addr = w * num_lines + index * line_size + i; - __asm__ __volatile__("licw %0, %1\n\t" - : "=a"(data) : "a"(addr)); - printk(" %#010lx", data); - } - } - printk ("\n"); -} - -void dump_cache_tags(void) -{ - printk("Instruction cache\n"); - dump_cache_tag(0, -1); - printk("Data cache\n"); - dump_cache_tag(1, -1); -} - -#endif diff --git a/arch/xtensa/platform-iss/console.c b/arch/xtensa/platform-iss/console.c index 5c947ca..2f4f20f 100644 --- a/arch/xtensa/platform-iss/console.c +++ b/arch/xtensa/platform-iss/console.c @@ -25,11 +25,15 @@ #include <asm/uaccess.h> #include <asm/irq.h> -#include <xtensa/simcall.h> +#include <asm/platform/simcall.h> #include <linux/tty.h> #include <linux/tty_flip.h> +#ifdef SERIAL_INLINE +#define _INLINE_ inline +#endif + #define SERIAL_MAX_NUM_LINES 1 #define SERIAL_TIMER_VALUE (20 * HZ) @@ -191,7 +195,7 @@ static int rs_read_proc(char *page, char **start, off_t off, int count, } -static const struct tty_operations serial_ops = { +static struct tty_operations serial_ops = { .open = rs_open, .close = rs_close, .write = rs_write, diff --git a/arch/xtensa/platform-iss/network.c b/arch/xtensa/platform-iss/network.c index 15d6441..8ebfc87 100644 --- a/arch/xtensa/platform-iss/network.c +++ b/arch/xtensa/platform-iss/network.c @@ -34,7 +34,7 @@ #include <linux/timer.h> #include <linux/platform_device.h> -#include <xtensa/simcall.h> +#include <asm/platform/simcall.h> #define DRIVER_NAME "iss-netdev" #define ETH_MAX_PACKET 1500 |