diff options
Diffstat (limited to 'drivers/gpu/pvr')
| -rw-r--r-- | drivers/gpu/pvr/bridged_pvr_bridge.c | 37 | ||||
| -rw-r--r-- | drivers/gpu/pvr/devicemem.c | 8 | ||||
| -rw-r--r-- | drivers/gpu/pvr/ion.c | 5 | ||||
| -rw-r--r-- | drivers/gpu/pvr/ion.h | 2 | ||||
| -rw-r--r-- | drivers/gpu/pvr/mm.c | 48 | ||||
| -rw-r--r-- | drivers/gpu/pvr/omap4/syslocal.h | 4 | ||||
| -rw-r--r-- | drivers/gpu/pvr/pdump_km.h | 2 | ||||
| -rw-r--r-- | drivers/gpu/pvr/pvr_bridge.h | 22 | ||||
| -rw-r--r-- | drivers/gpu/pvr/pvr_bridge_k.c | 11 | ||||
| -rw-r--r-- | drivers/gpu/pvr/pvr_uaccess.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/pvr/pvrversion.h | 6 | ||||
| -rw-r--r-- | drivers/gpu/pvr/queue.c | 18 | ||||
| -rw-r--r-- | drivers/gpu/pvr/refcount.h | 40 | ||||
| -rw-r--r-- | drivers/gpu/pvr/servicesint.h | 10 | ||||
| -rw-r--r-- | drivers/gpu/pvr/sgx/bridged_sgx_bridge.c | 108 | ||||
| -rw-r--r-- | drivers/gpu/pvr/sgx/sgxinit.c | 40 | ||||
| -rw-r--r-- | drivers/gpu/pvr/sgx/sgxpower.c | 1 | ||||
| -rw-r--r-- | drivers/gpu/pvr/sgx/sgxreset.c | 3 | ||||
| -rw-r--r-- | drivers/gpu/pvr/sgx/sgxutils.c | 527 | ||||
| -rw-r--r-- | drivers/gpu/pvr/sgx/sgxutils.h | 37 | ||||
| -rw-r--r-- | drivers/gpu/pvr/sgx_bridge.h | 70 | ||||
| -rw-r--r-- | drivers/gpu/pvr/sgxerrata.h | 3 | ||||
| -rw-r--r-- | drivers/gpu/pvr/sgxfeaturedefs.h | 11 |
23 files changed, 792 insertions, 222 deletions
diff --git a/drivers/gpu/pvr/bridged_pvr_bridge.c b/drivers/gpu/pvr/bridged_pvr_bridge.c index 7a84ee8..e7ff189 100644 --- a/drivers/gpu/pvr/bridged_pvr_bridge.c +++ b/drivers/gpu/pvr/bridged_pvr_bridge.c @@ -3568,40 +3568,6 @@ PVRSRVMapMemInfoMemBW(IMG_UINT32 ui32BridgeID, -static IMG_INT -MMU_GetPDDevPAddrBW(IMG_UINT32 ui32BridgeID, - PVRSRV_BRIDGE_IN_GETMMU_PD_DEVPADDR *psGetMmuPDDevPAddrIN, - PVRSRV_BRIDGE_OUT_GETMMU_PD_DEVPADDR *psGetMmuPDDevPAddrOUT, - PVRSRV_PER_PROCESS_DATA *psPerProc) -{ - IMG_HANDLE hDevMemContextInt; - - PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_GETMMU_PD_DEVPADDR); - - psGetMmuPDDevPAddrOUT->eError = - PVRSRVLookupHandle(psPerProc->psHandleBase, &hDevMemContextInt, - psGetMmuPDDevPAddrIN->hDevMemContext, - PVRSRV_HANDLE_TYPE_DEV_MEM_CONTEXT); - if(psGetMmuPDDevPAddrOUT->eError != PVRSRV_OK) - { - return 0; - } - - psGetMmuPDDevPAddrOUT->sPDDevPAddr = - BM_GetDeviceNode(hDevMemContextInt)->pfnMMUGetPDDevPAddr(BM_GetMMUContextFromMemContext(hDevMemContextInt)); - if(psGetMmuPDDevPAddrOUT->sPDDevPAddr.uiAddr) - { - psGetMmuPDDevPAddrOUT->eError = PVRSRV_OK; - } - else - { - psGetMmuPDDevPAddrOUT->eError = PVRSRV_ERROR_INVALID_PHYS_ADDR; - } - return 0; -} - - - IMG_INT DummyBW(IMG_UINT32 ui32BridgeID, IMG_VOID *psBridgeIn, @@ -4729,9 +4695,6 @@ CommonBridgeInit(IMG_VOID) SetDispatchTableEntry(PVRSRV_BRIDGE_FREE_SHARED_SYS_MEM, PVRSRVFreeSharedSysMemoryBW); SetDispatchTableEntry(PVRSRV_BRIDGE_MAP_MEMINFO_MEM, PVRSRVMapMemInfoMemBW); - - SetDispatchTableEntry(PVRSRV_BRIDGE_GETMMU_PD_DEVPADDR, MMU_GetPDDevPAddrBW); - SetDispatchTableEntry(PVRSRV_BRIDGE_INITSRV_CONNECT, &PVRSRVInitSrvConnectBW); SetDispatchTableEntry(PVRSRV_BRIDGE_INITSRV_DISCONNECT, &PVRSRVInitSrvDisconnectBW); diff --git a/drivers/gpu/pvr/devicemem.c b/drivers/gpu/pvr/devicemem.c index cd22faa..8e527e9 100644 --- a/drivers/gpu/pvr/devicemem.c +++ b/drivers/gpu/pvr/devicemem.c @@ -1766,8 +1766,12 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVMapDeviceClassMemoryKM(PVRSRV_PER_PROCESS_DATA * #if defined(SUPPORT_PDUMP_MULTI_PROCESS) - PDUMPCOMMENT("Dump display surface"); - PDUMPMEM(IMG_NULL, psMemInfo, ui32Offset, psMemInfo->uAllocSize, PDUMP_FLAGS_CONTINUOUS, ((BM_BUF*)psMemInfo->sMemBlk.hBuffer)->pMapping); + if(psMemInfo->pvLinAddrKM) + { + + PDUMPCOMMENT("Dump display surface"); + PDUMPMEM(IMG_NULL, psMemInfo, ui32Offset, psMemInfo->uAllocSize, PDUMP_FLAGS_CONTINUOUS, ((BM_BUF*)psMemInfo->sMemBlk.hBuffer)->pMapping); + } #endif return PVRSRV_OK; diff --git a/drivers/gpu/pvr/ion.c b/drivers/gpu/pvr/ion.c index 36b6f59..b00fdb1 100644 --- a/drivers/gpu/pvr/ion.c +++ b/drivers/gpu/pvr/ion.c @@ -44,7 +44,7 @@ extern struct ion_client *gpsIONClient; void PVRSRVExportFDToIONHandles(int fd, struct ion_client **client, - struct ion_handle *handles[2]) + struct ion_handle *handles[2]) { PVRSRV_FILE_PRIVATE_DATA *psPrivateData; PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo; @@ -99,7 +99,6 @@ err_unlock: /* Allow PVRSRV clients to communicate with srvkm again */ LinuxUnLockMutex(&gPVRSRVLock); } -EXPORT_SYMBOL(PVRSRVExportFDToIONHandles); struct ion_handle * PVRSRVExportFDToIONHandle(int fd, struct ion_client **client) @@ -108,4 +107,6 @@ PVRSRVExportFDToIONHandle(int fd, struct ion_client **client) PVRSRVExportFDToIONHandles(fd, client, psHandles); return psHandles[0]; } + +EXPORT_SYMBOL(PVRSRVExportFDToIONHandles); EXPORT_SYMBOL(PVRSRVExportFDToIONHandle); diff --git a/drivers/gpu/pvr/ion.h b/drivers/gpu/pvr/ion.h index bbe3e56..1ee3821 100644 --- a/drivers/gpu/pvr/ion.h +++ b/drivers/gpu/pvr/ion.h @@ -31,7 +31,7 @@ #include <linux/omap_ion.h> void PVRSRVExportFDToIONHandles(int fd, struct ion_client **client, - struct ion_handle *handles[2]); + struct ion_handle *handles[2]); struct ion_handle *PVRSRVExportFDToIONHandle(int fd, struct ion_client **client); diff --git a/drivers/gpu/pvr/mm.c b/drivers/gpu/pvr/mm.c index 77f6006..fa3f7a3 100644 --- a/drivers/gpu/pvr/mm.c +++ b/drivers/gpu/pvr/mm.c @@ -1096,7 +1096,7 @@ NewIONLinuxMemArea(IMG_UINT32 ui32Bytes, IMG_UINT32 ui32AreaFlags, u32 *pu32PageAddrs[2] = { NULL, NULL }; IMG_UINT32 i, ui32NumHandlesPerFd; IMG_BYTE *pbPrivData = pvPrivData; - IMG_CPU_PHYADDR *pCPUPhysAddrs; + IMG_CPU_PHYADDR *pCPUPhysAddrs; int iNumPages[2] = { 0, 0 }; LinuxMemArea *psLinuxMemArea; @@ -1109,43 +1109,42 @@ NewIONLinuxMemArea(IMG_UINT32 ui32Bytes, IMG_UINT32 ui32AreaFlags, BUG_ON(ui32PrivDataLength != ui32AllocDataLen && - ui32PrivDataLength != ui32AllocDataLen * 2); + ui32PrivDataLength != ui32AllocDataLen * 2); ui32NumHandlesPerFd = ui32PrivDataLength / ui32AllocDataLen; - for (i = 0; i < ui32NumHandlesPerFd; i++) + + for(i = 0; i < ui32NumHandlesPerFd; i++) { - memcpy(&asAllocData[i], &pbPrivData[i * ui32AllocDataLen], - ui32AllocDataLen); + memcpy(&asAllocData[i], &pbPrivData[i * ui32AllocDataLen], ui32AllocDataLen); - if (omap_ion_tiler_alloc(gpsIONClient, &asAllocData[i]) < 0) + if(omap_ion_tiler_alloc(gpsIONClient, &asAllocData[i]) < 0) { - PVR_DPF((PVR_DBG_ERROR, "%s: Failed to allocate via ion_tiler", - __func__)); + PVR_DPF((PVR_DBG_ERROR, "%s: Failed to allocate via ion_tiler", __func__)); goto err_free; } - if (omap_tiler_pages(gpsIONClient, asAllocData[i].handle, &iNumPages[i], - &pu32PageAddrs[i]) < 0) + if(omap_tiler_pages(gpsIONClient, asAllocData[i].handle, &iNumPages[i], + &pu32PageAddrs[i]) < 0) { - PVR_DPF((PVR_DBG_ERROR, "%s: Failed to compute tiler pages", - __func__)); + PVR_DPF((PVR_DBG_ERROR, "%s: Failed to compute tiler pages", __func__)); goto err_free; } } + BUG_ON(ui32Bytes != (iNumPages[0] + iNumPages[1]) * PAGE_SIZE); BUG_ON(sizeof(IMG_CPU_PHYADDR) != sizeof(int)); - pCPUPhysAddrs = vmalloc(sizeof(IMG_CPU_PHYADDR) * (iNumPages[0] + - iNumPages[1])); - if (!pCPUPhysAddrs) + + pCPUPhysAddrs = vmalloc(sizeof(IMG_CPU_PHYADDR) * (iNumPages[0] + iNumPages[1])); + if(!pCPUPhysAddrs) { PVR_DPF((PVR_DBG_ERROR, "%s: Failed to allocate page list", __func__)); goto err_free; } - for (i = 0; i < iNumPages[0]; i++) + for(i = 0; i < iNumPages[0]; i++) pCPUPhysAddrs[i].uiAddr = pu32PageAddrs[0][i]; - for (i = 0; i < iNumPages[1]; i++) + for(i = 0; i < iNumPages[1]; i++) pCPUPhysAddrs[iNumPages[0] + i].uiAddr = pu32PageAddrs[1][i]; #if defined(DEBUG_LINUX_MEMORY_ALLOCATIONS) @@ -1160,11 +1159,8 @@ NewIONLinuxMemArea(IMG_UINT32 ui32Bytes, IMG_UINT32 ui32AreaFlags, ); #endif - for (i = 0; i < 2; i++) - { - psLinuxMemArea->uData.sIONTilerAlloc.psIONHandle[i] = - asAllocData[i].handle; - } + for(i = 0; i < 2; i++) + psLinuxMemArea->uData.sIONTilerAlloc.psIONHandle[i] = asAllocData[i].handle; psLinuxMemArea->eAreaType = LINUX_MEM_AREA_ION; psLinuxMemArea->uData.sIONTilerAlloc.pCPUPhysAddrs = pCPUPhysAddrs; @@ -1206,15 +1202,15 @@ FreeIONLinuxMemArea(LinuxMemArea *psLinuxMemArea) __FILE__, __LINE__); #endif - for (i = 0; i < 2; i++) + for(i = 0; i < 2; i++) { - if (!psLinuxMemArea->uData.sIONTilerAlloc.psIONHandle[i]) + if(!psLinuxMemArea->uData.sIONTilerAlloc.psIONHandle[i]) break; - ion_free(gpsIONClient, - psLinuxMemArea->uData.sIONTilerAlloc.psIONHandle[i]); + ion_free(gpsIONClient, psLinuxMemArea->uData.sIONTilerAlloc.psIONHandle[i]); psLinuxMemArea->uData.sIONTilerAlloc.psIONHandle[i] = IMG_NULL; } + vfree(psLinuxMemArea->uData.sIONTilerAlloc.pCPUPhysAddrs); psLinuxMemArea->uData.sIONTilerAlloc.pCPUPhysAddrs = IMG_NULL; diff --git a/drivers/gpu/pvr/omap4/syslocal.h b/drivers/gpu/pvr/omap4/syslocal.h index 7f8bb56..6e5ed43 100644 --- a/drivers/gpu/pvr/omap4/syslocal.h +++ b/drivers/gpu/pvr/omap4/syslocal.h @@ -82,12 +82,10 @@ #endif #if defined(__linux__) -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)) && defined(SGX_OCP_REGS_ENABLED) -#if !defined(SGX544) /*FIXME: Workaround for OMAP4470 */ +#if defined(SGX_OCP_REGS_ENABLED) #define SGX_OCP_NO_INT_BYPASS #endif #endif -#endif #if defined (__cplusplus) extern "C" { diff --git a/drivers/gpu/pvr/pdump_km.h b/drivers/gpu/pvr/pdump_km.h index 224e922..6c516e0 100644 --- a/drivers/gpu/pvr/pdump_km.h +++ b/drivers/gpu/pvr/pdump_km.h @@ -337,6 +337,7 @@ extern IMG_UINT32 g_ui32EveryLineCounter; #define PDUMPMALLOCPAGETABLE PDumpMallocPageTable #define PDUMPSETMMUCONTEXT PDumpSetMMUContext #define PDUMPCLEARMMUCONTEXT PDumpClearMMUContext + #define PDUMPPDDEVPADDR PDumpPDDevPAddrKM #define PDUMPFREEPAGES PDumpFreePages #define PDUMPFREEPAGETABLE PDumpFreePageTable #define PDUMPPDREG PDumpPDReg @@ -373,6 +374,7 @@ extern IMG_UINT32 g_ui32EveryLineCounter; #define PDUMPMALLOCPAGETABLE(args...) #define PDUMPSETMMUCONTEXT(args...) #define PDUMPCLEARMMUCONTEXT(args...) + #define PDUMPPDDEVPADDR(args...) #define PDUMPFREEPAGES(args...) #define PDUMPFREEPAGETABLE(args...) #define PDUMPPDREG(args...) diff --git a/drivers/gpu/pvr/pvr_bridge.h b/drivers/gpu/pvr/pvr_bridge.h index d3e5916..443ad1e 100644 --- a/drivers/gpu/pvr/pvr_bridge.h +++ b/drivers/gpu/pvr/pvr_bridge.h @@ -191,11 +191,7 @@ extern "C" { #define PVRSRV_BRIDGE_UNMAP_MEMINFO_MEM PVRSRV_IOWR(PVRSRV_BRIDGE_SHAREDMEM_CMD_FIRST+3) #define PVRSRV_BRIDGE_SHAREDMEM_CMD_LAST (PVRSRV_BRIDGE_SHAREDMEM_CMD_FIRST+3) -#define PVRSRV_BRIDGE_SERVICES4_TMP_CMD_FIRST (PVRSRV_BRIDGE_SHAREDMEM_CMD_LAST+1) -#define PVRSRV_BRIDGE_GETMMU_PD_DEVPADDR PVRSRV_IOWR(PVRSRV_BRIDGE_SERVICES4_TMP_CMD_FIRST+0) -#define PVRSRV_BRIDGE_SERVICES4_TMP_CMD_LAST (PVRSRV_BRIDGE_SERVICES4_TMP_CMD_FIRST+0) - -#define PVRSRV_BRIDGE_INITSRV_CMD_FIRST (PVRSRV_BRIDGE_SERVICES4_TMP_CMD_LAST+1) +#define PVRSRV_BRIDGE_INITSRV_CMD_FIRST (PVRSRV_BRIDGE_SHAREDMEM_CMD_LAST+1) #define PVRSRV_BRIDGE_INITSRV_CONNECT PVRSRV_IOWR(PVRSRV_BRIDGE_INITSRV_CMD_FIRST+0) #define PVRSRV_BRIDGE_INITSRV_DISCONNECT PVRSRV_IOWR(PVRSRV_BRIDGE_INITSRV_CMD_FIRST+1) #define PVRSRV_BRIDGE_INITSRV_CMD_LAST (PVRSRV_BRIDGE_INITSRV_CMD_FIRST+1) @@ -1595,22 +1591,6 @@ typedef struct PVRSRV_BRIDGE_OUT_UNMAP_MEMINFO_MEM_TAG PVRSRV_ERROR eError; }PVRSRV_BRIDGE_OUT_UNMAP_MEMINFO_MEM; -typedef struct PVRSRV_BRIDGE_IN_GETMMU_PD_DEVPADDR_TAG -{ - IMG_UINT32 ui32BridgeFlags; -#if defined (SUPPORT_SID_INTERFACE) - IMG_SID hDevMemContext; -#else - IMG_HANDLE hDevMemContext; -#endif -}PVRSRV_BRIDGE_IN_GETMMU_PD_DEVPADDR; - -typedef struct PVRSRV_BRIDGE_OUT_GETMMU_PD_DEVPADDR_TAG -{ - IMG_DEV_PHYADDR sPDDevPAddr; - PVRSRV_ERROR eError; -}PVRSRV_BRIDGE_OUT_GETMMU_PD_DEVPADDR; - typedef struct PVRSRV_BRIDGE_IN_EVENT_OBJECT_WAI_TAG { IMG_UINT32 ui32BridgeFlags; diff --git a/drivers/gpu/pvr/pvr_bridge_k.c b/drivers/gpu/pvr/pvr_bridge_k.c index 6d51200..2002f64 100644 --- a/drivers/gpu/pvr/pvr_bridge_k.c +++ b/drivers/gpu/pvr/pvr_bridge_k.c @@ -382,12 +382,19 @@ PVRSRV_BridgeDispatchKM(struct file *pFile, unsigned int unref__ ioctlCmd, unsig PVRSRV_BRIDGE_OUT_EXPORTDEVICEMEM *psExportDeviceMemOUT = (PVRSRV_BRIDGE_OUT_EXPORTDEVICEMEM *)psBridgePackageKM->pvParamOut; PVRSRV_FILE_PRIVATE_DATA *psPrivateData = PRIVATE_DATA(pFile); + IMG_HANDLE hMemInfo; PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo; + if (pvr_get_user(hMemInfo, &psExportDeviceMemOUT->hMemInfo) != 0) + { + err = -EFAULT; + goto unlock_and_return; + } + if(PVRSRVLookupHandle(KERNEL_HANDLE_BASE, (IMG_PVOID *)&psKernelMemInfo, - psExportDeviceMemOUT->hMemInfo, + hMemInfo, PVRSRV_HANDLE_TYPE_MEM_INFO) != PVRSRV_OK) { PVR_DPF((PVR_DBG_ERROR, "%s: Failed to look up export handle", __FUNCTION__)); @@ -398,7 +405,7 @@ PVRSRV_BridgeDispatchKM(struct file *pFile, unsigned int unref__ ioctlCmd, unsig PVRSRVKernelMemInfoIncRef(psKernelMemInfo); - psPrivateData->hKernelMemInfo = psExportDeviceMemOUT->hMemInfo; + psPrivateData->hKernelMemInfo = hMemInfo; #if defined(SUPPORT_MEMINFO_IDS) psPrivateData->ui64Stamp = ++ui64Stamp; diff --git a/drivers/gpu/pvr/pvr_uaccess.h b/drivers/gpu/pvr/pvr_uaccess.h index 4b7114e..6e7f1d3 100644 --- a/drivers/gpu/pvr/pvr_uaccess.h +++ b/drivers/gpu/pvr/pvr_uaccess.h @@ -65,6 +65,7 @@ static inline unsigned long pvr_copy_from_user(void *pvTo, const void __user *pv } #define pvr_put_user put_user +#define pvr_get_user get_user #endif diff --git a/drivers/gpu/pvr/pvrversion.h b/drivers/gpu/pvr/pvrversion.h index 1065b1c..fcdaa4d 100644 --- a/drivers/gpu/pvr/pvrversion.h +++ b/drivers/gpu/pvr/pvrversion.h @@ -36,7 +36,7 @@ #define PVRVERSION_FAMILY "sgxddk" #define PVRVERSION_BRANCHNAME "1.8" -#define PVRVERSION_BUILD 785978 +#define PVRVERSION_BUILD 796887 #define PVRVERSION_BSCONTROL "CustomerGoogle_Android_ogles1_ogles2_GPL" #define PVRVERSION_STRING "CustomerGoogle_Android_ogles1_ogles2_GPL sgxddk 18 1.8@" PVR_STR2(PVRVERSION_BUILD) @@ -44,8 +44,8 @@ #define COPYRIGHT_TXT "Copyright (c) Imagination Technologies Ltd. All Rights Reserved." -#define PVRVERSION_BUILD_HI 78 -#define PVRVERSION_BUILD_LO 5978 +#define PVRVERSION_BUILD_HI 79 +#define PVRVERSION_BUILD_LO 6887 #define PVRVERSION_STRING_NUMERIC PVR_STR2(PVRVERSION_MAJ) "." PVR_STR2(PVRVERSION_MIN) "." PVR_STR2(PVRVERSION_BUILD_HI) "." PVR_STR2(PVRVERSION_BUILD_LO) #endif /* _PVRVERSION_H_ */ diff --git a/drivers/gpu/pvr/queue.c b/drivers/gpu/pvr/queue.c index 4682094..3bfd6c6 100644 --- a/drivers/gpu/pvr/queue.c +++ b/drivers/gpu/pvr/queue.c @@ -25,6 +25,7 @@ ******************************************************************************/ #include "services_headers.h" +#include "pvr_bridge_km.h" #include "lists.h" #include "ttrace.h" @@ -625,6 +626,8 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVInsertCommandKM(PVRSRV_QUEUE_INFO *psQueue, psCommand->psDstSync[i].ui32WriteOpsPending = PVRSRVGetWriteOpsPending(apsDstSync[i], IMG_FALSE); psCommand->psDstSync[i].ui32ReadOps2Pending = PVRSRVGetReadOpsPending(apsDstSync[i], IMG_FALSE); + PVRSRVKernelSyncInfoIncRef(apsDstSync[i], IMG_NULL); + PVR_DPF((PVR_DBG_MESSAGE, "PVRSRVInsertCommandKM: Dst %u RO-VA:0x%x WO-VA:0x%x ROP:0x%x WOP:0x%x", i, psCommand->psDstSync[i].psKernelSyncInfoKM->sReadOps2CompleteDevVAddr.uiAddr, psCommand->psDstSync[i].psKernelSyncInfoKM->sWriteOpsCompleteDevVAddr.uiAddr, @@ -642,6 +645,8 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVInsertCommandKM(PVRSRV_QUEUE_INFO *psQueue, psCommand->psSrcSync[i].ui32WriteOpsPending = PVRSRVGetWriteOpsPending(apsSrcSync[i], IMG_TRUE); psCommand->psSrcSync[i].ui32ReadOps2Pending = PVRSRVGetReadOpsPending(apsSrcSync[i], IMG_TRUE); + PVRSRVKernelSyncInfoIncRef(apsSrcSync[i], IMG_NULL); + PVR_DPF((PVR_DBG_MESSAGE, "PVRSRVInsertCommandKM: Src %u RO-VA:0x%x WO-VA:0x%x ROP:0x%x WOP:0x%x", i, psCommand->psSrcSync[i].psKernelSyncInfoKM->sReadOps2CompleteDevVAddr.uiAddr, psCommand->psSrcSync[i].psKernelSyncInfoKM->sWriteOpsCompleteDevVAddr.uiAddr, @@ -1003,6 +1008,12 @@ IMG_VOID PVRSRVCommandCompleteKM(IMG_HANDLE hCmdCookie, { psCmdCompleteData->psDstSync[i].psKernelSyncInfoKM->psSyncData->ui32WriteOpsComplete++; + PVRSRVKernelSyncInfoDecRef(psCmdCompleteData->psDstSync[i].psKernelSyncInfoKM, IMG_NULL); + if (psCmdCompleteData->psDstSync[i].psKernelSyncInfoKM->ui32RefCount == 0) + { + PVRSRVFreeSyncInfoKM(psCmdCompleteData->psDstSync[i].psKernelSyncInfoKM); + } + PVR_TTRACE_SYNC_OBJECT(PVRSRV_TRACE_GROUP_QUEUE, QUEUE_TOKEN_UPDATE_DST, psCmdCompleteData->psDstSync[i].psKernelSyncInfoKM, PVRSRV_SYNCOP_COMPLETE); @@ -1019,6 +1030,12 @@ IMG_VOID PVRSRVCommandCompleteKM(IMG_HANDLE hCmdCookie, { psCmdCompleteData->psSrcSync[i].psKernelSyncInfoKM->psSyncData->ui32ReadOps2Complete++; + PVRSRVKernelSyncInfoDecRef(psCmdCompleteData->psSrcSync[i].psKernelSyncInfoKM, IMG_NULL); + if (psCmdCompleteData->psSrcSync[i].psKernelSyncInfoKM->ui32RefCount == 0) + { + PVRSRVFreeSyncInfoKM(psCmdCompleteData->psSrcSync[i].psKernelSyncInfoKM); + } + PVR_TTRACE_SYNC_OBJECT(PVRSRV_TRACE_GROUP_QUEUE, QUEUE_TOKEN_UPDATE_SRC, psCmdCompleteData->psSrcSync[i].psKernelSyncInfoKM, PVRSRV_SYNCOP_COMPLETE); @@ -1185,6 +1202,7 @@ PVRSRV_ERROR PVRSRVRemoveCmdProcListKM(IMG_UINT32 ui32DevIndex, if (psCmdCompleteData != IMG_NULL) { + PVR_ASSERT(psCmdCompleteData->bInUse == IMG_FALSE); OSFreeMem(PVRSRV_OS_NON_PAGEABLE_HEAP, psCmdCompleteData->ui32AllocSize, psCmdCompleteData, IMG_NULL); psDeviceCommandData[ui32CmdTypeCounter].apsCmdCompleteData[ui32CmdCounter] = IMG_NULL; diff --git a/drivers/gpu/pvr/refcount.h b/drivers/gpu/pvr/refcount.h index d2fd9c7..1090aa4 100644 --- a/drivers/gpu/pvr/refcount.h +++ b/drivers/gpu/pvr/refcount.h @@ -100,6 +100,26 @@ static INLINE void PVRSRVKernelMemInfoDecRef(PVRSRV_KERNEL_MEM_INFO *psKernelMem psKernelMemInfo->ui32RefCount--; } +static INLINE void PVRSRVBMBufIncRef(BM_BUF *pBuf) +{ + pBuf->ui32RefCount++; +} + +static INLINE void PVRSRVBMBufDecRef(BM_BUF *pBuf) +{ + pBuf->ui32RefCount--; +} + +static INLINE void PVRSRVBMBufIncExport(BM_BUF *pBuf) +{ + pBuf->ui32ExportCount++; +} + +static INLINE void PVRSRVBMBufDecExport(BM_BUF *pBuf) +{ + pBuf->ui32ExportCount--; +} + #if defined(__linux__) /* mmap refcounting is Linux specific */ @@ -125,26 +145,6 @@ static INLINE void PVRSRVOffsetStructDecMapped(PKV_OFFSET_STRUCT psOffsetStruct) psOffsetStruct->ui32Mapped--; } -static INLINE void PVRSRVBMBufIncRef(BM_BUF *pBuf) -{ - pBuf->ui32RefCount++; -} - -static INLINE void PVRSRVBMBufDecRef(BM_BUF *pBuf) -{ - pBuf->ui32RefCount--; -} - -static INLINE void PVRSRVBMBufIncExport(BM_BUF *pBuf) -{ - pBuf->ui32ExportCount++; -} - -static INLINE void PVRSRVBMBufDecExport(BM_BUF *pBuf) -{ - pBuf->ui32ExportCount--; -} - #endif /* defined(__linux__) */ #endif /* defined(PVRSRV_REFCOUNT_DEBUG) */ diff --git a/drivers/gpu/pvr/servicesint.h b/drivers/gpu/pvr/servicesint.h index c9b565e..47a6aeb 100644 --- a/drivers/gpu/pvr/servicesint.h +++ b/drivers/gpu/pvr/servicesint.h @@ -341,16 +341,6 @@ PVRSRV_ERROR PVRSRVQueueCommand(IMG_HANDLE hQueueInfo, PVRSRV_COMMAND *psCommand); - -IMG_IMPORT PVRSRV_ERROR IMG_CALLCONV -PVRSRVGetMMUContextPDDevPAddr(const PVRSRV_CONNECTION *psConnection, -#if defined (SUPPORT_SID_INTERFACE) - IMG_SID hDevMemContext, -#else - IMG_HANDLE hDevMemContext, -#endif - IMG_DEV_PHYADDR *sPDDevPAddr); - IMG_IMPORT PVRSRV_ERROR IMG_CALLCONV PVRSRVAllocSharedSysMem(const PVRSRV_CONNECTION *psConnection, IMG_UINT32 ui32Flags, diff --git a/drivers/gpu/pvr/sgx/bridged_sgx_bridge.c b/drivers/gpu/pvr/sgx/bridged_sgx_bridge.c index f616d83..846b493 100644 --- a/drivers/gpu/pvr/sgx/bridged_sgx_bridge.c +++ b/drivers/gpu/pvr/sgx/bridged_sgx_bridge.c @@ -780,6 +780,90 @@ SGXSubmitTransferBW(IMG_UINT32 ui32BridgeID, return 0; } +static IMG_INT +SGXSetTransferContextPriorityBW(IMG_UINT32 ui32BridgeID, + PVRSRV_BRIDGE_IN_SGX_SET_TRANSFER_CONTEXT_PRIORITY *psSGXSetTransferContextPriorityIN, + PVRSRV_BRIDGE_RETURN *psRetOUT, + PVRSRV_PER_PROCESS_DATA *psPerProc) +{ + IMG_HANDLE hDevCookieInt; + IMG_HANDLE hTransferContextInt; + + PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SGX_SET_TRANSFER_CONTEXT_PRIORITY); + + psRetOUT->eError = + PVRSRVLookupHandle(psPerProc->psHandleBase, + &hDevCookieInt, + psSGXSetTransferContextPriorityIN->hDevCookie, + PVRSRV_HANDLE_TYPE_DEV_NODE); + + if(psRetOUT->eError != PVRSRV_OK) + { + return 0; + } + + psRetOUT->eError = + PVRSRVLookupHandle(psPerProc->psHandleBase, + &hTransferContextInt, + psSGXSetTransferContextPriorityIN->hHWTransferContext, + PVRSRV_HANDLE_TYPE_SGX_HW_TRANSFER_CONTEXT); + + if(psRetOUT->eError != PVRSRV_OK) + { + return 0; + } + + psRetOUT->eError = SGXSetTransferContextPriorityKM( + hDevCookieInt, + hTransferContextInt, + psSGXSetTransferContextPriorityIN->ui32Priority, + psSGXSetTransferContextPriorityIN->ui32OffsetOfPriorityField); + + return 0; +} + +static IMG_INT +SGXSetRenderContextPriorityBW(IMG_UINT32 ui32BridgeID, + PVRSRV_BRIDGE_IN_SGX_SET_RENDER_CONTEXT_PRIORITY *psSGXSetRenderContextPriorityIN, + PVRSRV_BRIDGE_RETURN *psRetOUT, + PVRSRV_PER_PROCESS_DATA *psPerProc) +{ + IMG_HANDLE hDevCookieInt; + IMG_HANDLE hRenderContextInt; + + PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SGX_SET_RENDER_CONTEXT_PRIORITY); + + psRetOUT->eError = + PVRSRVLookupHandle(psPerProc->psHandleBase, + &hDevCookieInt, + psSGXSetRenderContextPriorityIN->hDevCookie, + PVRSRV_HANDLE_TYPE_DEV_NODE); + + if(psRetOUT->eError != PVRSRV_OK) + { + return 0; + } + + psRetOUT->eError = + PVRSRVLookupHandle(psPerProc->psHandleBase, + &hRenderContextInt, + psSGXSetRenderContextPriorityIN->hHWRenderContext, + PVRSRV_HANDLE_TYPE_SGX_HW_RENDER_CONTEXT); + + if(psRetOUT->eError != PVRSRV_OK) + { + return 0; + } + + psRetOUT->eError = SGXSetRenderContextPriorityKM( + hDevCookieInt, + hRenderContextInt, + psSGXSetRenderContextPriorityIN->ui32Priority, + psSGXSetRenderContextPriorityIN->ui32OffsetOfPriorityField); + + return 0; +} + #if defined(SGX_FEATURE_2D_HARDWARE) static IMG_INT @@ -2176,8 +2260,12 @@ SGXRegisterHWRenderContextBW(IMG_UINT32 ui32BridgeID, hHWRenderContextInt = SGXRegisterHWRenderContextKM(hDevCookieInt, - &psSGXRegHWRenderContextIN->sHWRenderContextDevVAddr, - psPerProc); + psSGXRegHWRenderContextIN->pHWRenderContextCpuVAddr, + psSGXRegHWRenderContextIN->ui32HWRenderContextSize, + psSGXRegHWRenderContextIN->ui32OffsetToPDDevPAddr, + psSGXRegHWRenderContextIN->hDevMemContext, + &psSGXRegHWRenderContextOUT->sHWRenderContextDevVAddr, + psPerProc); if (hHWRenderContextInt == IMG_NULL) { @@ -2258,7 +2346,11 @@ SGXRegisterHWTransferContextBW(IMG_UINT32 ui32BridgeID, hHWTransferContextInt = SGXRegisterHWTransferContextKM(hDevCookieInt, - &psSGXRegHWTransferContextIN->sHWTransferContextDevVAddr, + psSGXRegHWTransferContextIN->pHWTransferContextCpuVAddr, + psSGXRegHWTransferContextIN->ui32HWTransferContextSize, + psSGXRegHWTransferContextIN->ui32OffsetToPDDevPAddr, + psSGXRegHWTransferContextIN->hDevMemContext, + &psSGXRegHWTransferContextOUT->sHWTransferContextDevVAddr, psPerProc); if (hHWTransferContextInt == IMG_NULL) @@ -2345,7 +2437,11 @@ SGXRegisterHW2DContextBW(IMG_UINT32 ui32BridgeID, hHW2DContextInt = SGXRegisterHW2DContextKM(hDevCookieInt, - &psSGXRegHW2DContextIN->sHW2DContextDevVAddr, + psSGXRegHW2DContextIN->pHW2DContextCpuVAddr, + psSGXRegHW2DContextIN->ui32HW2DContextSize, + psSGXRegHW2DContextIN->ui32OffsetToPDDevPAddr, + psSGXRegHW2DContextIN->hDevMemContext, + &psSGXRegHW2DContextOUT->sHW2DContextDevVAddr, psPerProc); if (hHW2DContextInt == IMG_NULL) @@ -3627,8 +3723,6 @@ IMG_VOID SetSGXDispatchTableEntry(IMG_VOID) SetDispatchTableEntry(PVRSRV_BRIDGE_SGX_2DQUERYBLTSCOMPLETE, SGX2DQueryBlitsCompleteBW); - SetDispatchTableEntry(PVRSRV_BRIDGE_SGX_GETMMUPDADDR, DummyBW); - #if defined(TRANSFER_QUEUE) SetDispatchTableEntry(PVRSRV_BRIDGE_SGX_SUBMITTRANSFER, SGXSubmitTransferBW); #endif @@ -3653,6 +3747,8 @@ IMG_VOID SetSGXDispatchTableEntry(IMG_VOID) SetDispatchTableEntry(PVRSRV_BRIDGE_SGX_SCHEDULE_PROCESS_QUEUES, SGXScheduleProcessQueuesBW); SetDispatchTableEntry(PVRSRV_BRIDGE_SGX_READ_HWPERF_CB, SGXReadHWPerfCBBW); + SetDispatchTableEntry(PVRSRV_BRIDGE_SGX_SET_RENDER_CONTEXT_PRIORITY, SGXSetRenderContextPriorityBW); + SetDispatchTableEntry(PVRSRV_BRIDGE_SGX_SET_TRANSFER_CONTEXT_PRIORITY, SGXSetTransferContextPriorityBW); #if defined(PDUMP) SetDispatchTableEntry(PVRSRV_BRIDGE_SGX_PDUMP_BUFFER_ARRAY, SGXPDumpBufferArrayBW); diff --git a/drivers/gpu/pvr/sgx/sgxinit.c b/drivers/gpu/pvr/sgx/sgxinit.c index 934f88f..ac07571 100644 --- a/drivers/gpu/pvr/sgx/sgxinit.c +++ b/drivers/gpu/pvr/sgx/sgxinit.c @@ -52,7 +52,6 @@ #include "lists.h" #include "srvkm.h" #include "ttrace.h" - #define VAR(x) #x @@ -1003,6 +1002,19 @@ static PVRSRV_ERROR DevDeInitSGX (IMG_VOID *pvDeviceNode) } +#if defined(RESTRICTED_REGISTERS) && defined(SGX_FEATURE_MP) + +static IMG_VOID SGXDumpMasterDebugReg (PVRSRV_SGXDEV_INFO *psDevInfo, + IMG_CHAR *pszName, + IMG_UINT32 ui32RegAddr) +{ + IMG_UINT32 ui32RegVal; + ui32RegVal = OSReadHWReg(psDevInfo->pvRegsBaseKM, ui32RegAddr); + PVR_LOG(("(HYD) %s%08X", pszName, ui32RegVal)); +} + +#endif + static IMG_VOID SGXDumpDebugReg (PVRSRV_SGXDEV_INFO *psDevInfo, IMG_UINT32 ui32CoreNum, IMG_CHAR *pszName, @@ -1030,7 +1042,27 @@ IMG_VOID SGXDumpDebugInfo (PVRSRV_SGXDEV_INFO *psDevInfo, SGXDumpDebugReg(psDevInfo, 0, "EUR_CR_CORE_ID: ", EUR_CR_CORE_ID); SGXDumpDebugReg(psDevInfo, 0, "EUR_CR_CORE_REVISION: ", EUR_CR_CORE_REVISION); - +#if defined(RESTRICTED_REGISTERS) && defined(SGX_FEATURE_MP) + SGXDumpMasterDebugReg(psDevInfo, "EUR_CR_MASTER_BIF_INT_STAT: ", EUR_CR_MASTER_BIF_INT_STAT); + SGXDumpMasterDebugReg(psDevInfo, "EUR_CR_MASTER_BIF_FAULT: ",EUR_CR_MASTER_BIF_FAULT); + SGXDumpMasterDebugReg(psDevInfo, "EUR_CR_MASTER_CLKGATESTATUS2: ",EUR_CR_MASTER_CLKGATESTATUS2 ); + SGXDumpMasterDebugReg(psDevInfo, "EUR_CR_MASTER_VDM_PIM_STATUS: ",EUR_CR_MASTER_VDM_PIM_STATUS); + SGXDumpMasterDebugReg(psDevInfo, "EUR_CR_MASTER_BIF_BANK_SET: ",EUR_CR_MASTER_BIF_BANK_SET); + + SGXDumpMasterDebugReg(psDevInfo, "EUR_CR_MASTER_EVENT_STATUS: ",EUR_CR_MASTER_EVENT_STATUS); + SGXDumpMasterDebugReg(psDevInfo, "EUR_CR_MASTER_EVENT_STATUS2: ",EUR_CR_MASTER_EVENT_STATUS2); + SGXDumpMasterDebugReg(psDevInfo, "EUR_CR_MASTER_MP_PRIMITIVE: ",EUR_CR_MASTER_MP_PRIMITIVE); + SGXDumpMasterDebugReg(psDevInfo, "EUR_CR_MASTER_DPM_DPLIST_STATUS: ",EUR_CR_MASTER_DPM_DPLIST_STATUS); + SGXDumpMasterDebugReg(psDevInfo, "EUR_CR_MASTER_DPM_PROACTIVE_PIM_SPEC: ",EUR_CR_MASTER_DPM_PROACTIVE_PIM_SPEC); + SGXDumpMasterDebugReg(psDevInfo, "EUR_CR_MASTER_PAGE_MANAGEOP: ",EUR_CR_MASTER_DPM_PAGE_MANAGEOP); + SGXDumpMasterDebugReg(psDevInfo, "EUR_CR_MASTER_VDM_CONTEXT_STORE_SNAPSHOT: ",EUR_CR_MASTER_VDM_CONTEXT_STORE_SNAPSHOT); + SGXDumpMasterDebugReg(psDevInfo, "EUR_CR_MASTER_VDM_CONTEXT_LOAD_STATUS: ",EUR_CR_MASTER_VDM_CONTEXT_LOAD_STATUS); + SGXDumpMasterDebugReg(psDevInfo, "EUR_CR_MASTER_VDM_CONTEXT_STORE_STREAM: ",EUR_CR_MASTER_VDM_CONTEXT_STORE_STREAM); + SGXDumpMasterDebugReg(psDevInfo, "EUR_CR_MASTER_VDM_CONTEXT_STORE_STATUS: ",EUR_CR_MASTER_VDM_CONTEXT_STORE_STATUS); + SGXDumpMasterDebugReg(psDevInfo, "EUR_CR_MASTER_VDM_CONTEXT_STORE_STATE0: ",EUR_CR_MASTER_VDM_CONTEXT_STORE_STATE0); + SGXDumpMasterDebugReg(psDevInfo, "EUR_CR_MASTER_VDM_CONTEXT_STORE_STATE1: ",EUR_CR_MASTER_VDM_CONTEXT_STORE_STATE1); + SGXDumpMasterDebugReg(psDevInfo, "EUR_CR_MASTER_VDM_WAIT_FOR_KICK: ",EUR_CR_MASTER_VDM_WAIT_FOR_KICK); +#endif for (ui32CoreNum = 0; ui32CoreNum < SGX_FEATURE_MP_CORE_COUNT_3D; ui32CoreNum++) { @@ -1297,14 +1329,14 @@ IMG_VOID SGXOSTimer(IMG_VOID *pvData) ui32BIFCtrl = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL); OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32BIFCtrl | EUR_CR_BIF_CTRL_PAUSE_MASK); - OSWaitus(200 * 1000000 / psDevInfo->ui32CoreClockSpeed); + SGXWaitClocks(psDevInfo, 200); #endif bBRN31093Inval = IMG_TRUE; OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL_INVAL, EUR_CR_BIF_CTRL_INVAL_PTE_MASK); - OSWaitus(200 * 1000000 / psDevInfo->ui32CoreClockSpeed); + SGXWaitClocks(psDevInfo, 200); #if defined(FIX_HW_BRN_29997) diff --git a/drivers/gpu/pvr/sgx/sgxpower.c b/drivers/gpu/pvr/sgx/sgxpower.c index 696941f..b647b68 100644 --- a/drivers/gpu/pvr/sgx/sgxpower.c +++ b/drivers/gpu/pvr/sgx/sgxpower.c @@ -271,6 +271,7 @@ PVRSRV_ERROR SGXPrePowerState (IMG_HANDLE hDevHandle, IMG_FALSE) != PVRSRV_OK) { PVR_DPF((PVR_DBG_ERROR,"SGXPrePowerState: Wait for SGX ukernel power transition failed.")); + SGXDumpDebugInfo(psDevInfo, IMG_FALSE); PVR_DBG_BREAK; } #endif diff --git a/drivers/gpu/pvr/sgx/sgxreset.c b/drivers/gpu/pvr/sgx/sgxreset.c index 7050371..a027298 100644 --- a/drivers/gpu/pvr/sgx/sgxreset.c +++ b/drivers/gpu/pvr/sgx/sgxreset.c @@ -29,6 +29,7 @@ #include "services_headers.h" #include "sgxinfokm.h" #include "sgxconfig.h" +#include "sgxutils.h" #include "pdump_km.h" @@ -168,7 +169,7 @@ static IMG_VOID SGXResetSleep(PVRSRV_SGXDEV_INFO *psDevInfo, #endif - OSWaitus(100 * 1000000 / psDevInfo->ui32CoreClockSpeed); + SGXWaitClocks(psDevInfo, 100); if (bPDump) { PDUMPIDLWITHFLAGS(30, ui32PDUMPFlags); diff --git a/drivers/gpu/pvr/sgx/sgxutils.c b/drivers/gpu/pvr/sgx/sgxutils.c index c9a733b..db2d02e 100644 --- a/drivers/gpu/pvr/sgx/sgxutils.c +++ b/drivers/gpu/pvr/sgx/sgxutils.c @@ -563,11 +563,16 @@ PVRSRV_ERROR SGXScheduleCCBCommandKM(PVRSRV_DEVICE_NODE *psDeviceNode, { if (ui32CallerID == ISR_ID) { + SYS_DATA *psSysData; + psDeviceNode->bReProcessDeviceCommandComplete = IMG_TRUE; eError = PVRSRV_OK; + + SysAcquireData(&psSysData); + OSScheduleMISR(psSysData); } else { @@ -721,8 +726,8 @@ PVRSRV_ERROR SGXCleanupRequest(PVRSRV_DEVICE_NODE *psDeviceNode, typedef struct _SGX_HW_RENDER_CONTEXT_CLEANUP_ { PVRSRV_DEVICE_NODE *psDeviceNode; - IMG_DEV_VIRTADDR sHWRenderContextDevVAddr; - IMG_HANDLE hBlockAlloc; + PVRSRV_KERNEL_MEM_INFO *psHWRenderContextMemInfo; + IMG_HANDLE hBlockAlloc; PRESMAN_ITEM psResItem; } SGX_HW_RENDER_CONTEXT_CLEANUP; @@ -737,10 +742,15 @@ static PVRSRV_ERROR SGXCleanupHWRenderContextCallback(IMG_PVOID pvParam, PVR_UNREFERENCED_PARAMETER(ui32Param); eError = SGXCleanupRequest(psCleanup->psDeviceNode, - &psCleanup->sHWRenderContextDevVAddr, + &psCleanup->psHWRenderContextMemInfo->sDevVAddr, PVRSRV_CLEANUPCMD_RC, bForceCleanup); + + PVRSRVFreeDeviceMemKM(psCleanup->psDeviceNode, + psCleanup->psHWRenderContextMemInfo); + + OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, sizeof(SGX_HW_RENDER_CONTEXT_CLEANUP), psCleanup, @@ -753,7 +763,7 @@ static PVRSRV_ERROR SGXCleanupHWRenderContextCallback(IMG_PVOID pvParam, typedef struct _SGX_HW_TRANSFER_CONTEXT_CLEANUP_ { PVRSRV_DEVICE_NODE *psDeviceNode; - IMG_DEV_VIRTADDR sHWTransferContextDevVAddr; + PVRSRV_KERNEL_MEM_INFO *psHWTransferContextMemInfo; IMG_HANDLE hBlockAlloc; PRESMAN_ITEM psResItem; } SGX_HW_TRANSFER_CONTEXT_CLEANUP; @@ -769,10 +779,15 @@ static PVRSRV_ERROR SGXCleanupHWTransferContextCallback(IMG_PVOID pvParam, PVR_UNREFERENCED_PARAMETER(ui32Param); eError = SGXCleanupRequest(psCleanup->psDeviceNode, - &psCleanup->sHWTransferContextDevVAddr, + &psCleanup->psHWTransferContextMemInfo->sDevVAddr, PVRSRV_CLEANUPCMD_TC, bForceCleanup); + + PVRSRVFreeDeviceMemKM(psCleanup->psDeviceNode, + psCleanup->psHWTransferContextMemInfo); + + OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, sizeof(SGX_HW_TRANSFER_CONTEXT_CLEANUP), psCleanup, @@ -783,13 +798,26 @@ static PVRSRV_ERROR SGXCleanupHWTransferContextCallback(IMG_PVOID pvParam, } IMG_EXPORT -IMG_HANDLE SGXRegisterHWRenderContextKM(IMG_HANDLE psDeviceNode, - IMG_DEV_VIRTADDR *psHWRenderContextDevVAddr, +IMG_HANDLE SGXRegisterHWRenderContextKM(IMG_HANDLE hDeviceNode, + IMG_CPU_VIRTADDR *psHWRenderContextCpuVAddr, + IMG_UINT32 ui32HWRenderContextSize, + IMG_UINT32 ui32OffsetToPDDevPAddr, + IMG_HANDLE hDevMemContext, + IMG_DEV_VIRTADDR *psHWRenderContextDevVAddr, PVRSRV_PER_PROCESS_DATA *psPerProc) { PVRSRV_ERROR eError; IMG_HANDLE hBlockAlloc; SGX_HW_RENDER_CONTEXT_CLEANUP *psCleanup; + PVRSRV_DEVICE_NODE *psDeviceNode = (PVRSRV_DEVICE_NODE *)hDeviceNode; + DEVICE_MEMORY_INFO *psDevMemoryInfo; + DEVICE_MEMORY_HEAP_INFO *psHeapInfo; + IMG_HANDLE hDevMemContextInt; + MMU_CONTEXT *psMMUContext; + IMG_DEV_PHYADDR sPDDevPAddr; + int iPtrByte; + IMG_UINT8 *pSrc; + IMG_UINT8 *pDst; PRESMAN_ITEM psResItem; eError = OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP, @@ -801,12 +829,98 @@ IMG_HANDLE SGXRegisterHWRenderContextKM(IMG_HANDLE psDeviceNode, if (eError != PVRSRV_OK) { PVR_DPF((PVR_DBG_ERROR, "SGXRegisterHWRenderContextKM: Couldn't allocate memory for SGX_HW_RENDER_CONTEXT_CLEANUP structure")); - return IMG_NULL; + goto exit0; + } + + psDevMemoryInfo = &psDeviceNode->sDevMemoryInfo; + psHeapInfo = &psDevMemoryInfo->psDeviceMemoryHeap[SGX_KERNEL_DATA_HEAP_ID]; + + eError = PVRSRVAllocDeviceMemKM(hDeviceNode, + psPerProc, + psHeapInfo->hDevMemHeap, + PVRSRV_MEM_READ | PVRSRV_MEM_WRITE + | PVRSRV_MEM_NO_SYNCOBJ | PVRSRV_MEM_EDM_PROTECT + | PVRSRV_MEM_CACHE_CONSISTENT, + ui32HWRenderContextSize, + 32, + IMG_NULL, + 0, + &psCleanup->psHWRenderContextMemInfo, + "HW Render Context"); + + if (eError != PVRSRV_OK) + { + PVR_DPF((PVR_DBG_ERROR, "SGXRegisterHWRenderContextKM: Couldn't allocate device memory for HW Render Context")); + goto exit1; } + eError = OSCopyFromUser(psPerProc, + psCleanup->psHWRenderContextMemInfo->pvLinAddrKM, + psHWRenderContextCpuVAddr, + ui32HWRenderContextSize); + + if (eError != PVRSRV_OK) + { + PVR_DPF((PVR_DBG_ERROR, "SGXRegisterHWRenderContextKM: Couldn't copy user-mode copy of HWContext into device memory")); + goto exit2; + } + + + psHWRenderContextDevVAddr->uiAddr = psCleanup->psHWRenderContextMemInfo->sDevVAddr.uiAddr; + + + eError = PVRSRVLookupHandle(psPerProc->psHandleBase, + &hDevMemContextInt, + hDevMemContext, + PVRSRV_HANDLE_TYPE_DEV_MEM_CONTEXT); + + if (eError != PVRSRV_OK) + { + PVR_DPF((PVR_DBG_ERROR, "SGXRegisterHWRenderContextKM: Can't lookup DevMem Context")); + goto exit2; + } + + psMMUContext = BM_GetMMUContextFromMemContext(hDevMemContextInt); + sPDDevPAddr = psDeviceNode->pfnMMUGetPDDevPAddr(psMMUContext); + + + + + + + pSrc = (IMG_UINT8 *)&sPDDevPAddr; + pDst = (IMG_UINT8 *)psCleanup->psHWRenderContextMemInfo->pvLinAddrKM; + pDst += ui32OffsetToPDDevPAddr; + + for (iPtrByte = 0; iPtrByte < sizeof(IMG_DEV_PHYADDR); iPtrByte++) + { + pDst[iPtrByte] = pSrc[iPtrByte]; + } + +#if defined(PDUMP) + + PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_CONTINUOUS, "HW Render context struct"); + + PDUMPMEM( + IMG_NULL, + psCleanup->psHWRenderContextMemInfo, + 0, + ui32HWRenderContextSize, + PDUMP_FLAGS_CONTINUOUS, + MAKEUNIQUETAG(psCleanup->psHWRenderContextMemInfo)); + + + PDUMPCOMMENT("Page directory address in HW render context"); + PDUMPPDDEVPADDR( + psCleanup->psHWRenderContextMemInfo, + ui32OffsetToPDDevPAddr, + sPDDevPAddr, + MAKEUNIQUETAG(psCleanup->psHWRenderContextMemInfo), + PDUMP_PD_UNIQUETAG); +#endif + psCleanup->hBlockAlloc = hBlockAlloc; psCleanup->psDeviceNode = psDeviceNode; - psCleanup->sHWRenderContextDevVAddr = *psHWRenderContextDevVAddr; psResItem = ResManRegisterRes(psPerProc->hResManContext, RESMAN_TYPE_HW_RENDER_CONTEXT, @@ -814,21 +928,27 @@ IMG_HANDLE SGXRegisterHWRenderContextKM(IMG_HANDLE psDeviceNode, 0, &SGXCleanupHWRenderContextCallback); - if (psResItem == IMG_NULL) - { - PVR_DPF((PVR_DBG_ERROR, "SGXRegisterHWRenderContextKM: ResManRegisterRes failed")); - OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, - sizeof(SGX_HW_RENDER_CONTEXT_CLEANUP), - psCleanup, - psCleanup->hBlockAlloc); - - - return IMG_NULL; - } + if (psResItem == IMG_NULL) + { + PVR_DPF((PVR_DBG_ERROR, "SGXRegisterHWRenderContextKM: ResManRegisterRes failed")); + goto exit2; + } psCleanup->psResItem = psResItem; return (IMG_HANDLE)psCleanup; + +exit2: + PVRSRVFreeDeviceMemKM(hDeviceNode, + psCleanup->psHWRenderContextMemInfo); +exit1: + OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, + sizeof(SGX_HW_RENDER_CONTEXT_CLEANUP), + psCleanup, + psCleanup->hBlockAlloc); + +exit0: + return IMG_NULL; } IMG_EXPORT @@ -854,13 +974,26 @@ PVRSRV_ERROR SGXUnregisterHWRenderContextKM(IMG_HANDLE hHWRenderContext, IMG_BOO IMG_EXPORT -IMG_HANDLE SGXRegisterHWTransferContextKM(IMG_HANDLE psDeviceNode, - IMG_DEV_VIRTADDR *psHWTransferContextDevVAddr, +IMG_HANDLE SGXRegisterHWTransferContextKM(IMG_HANDLE hDeviceNode, + IMG_CPU_VIRTADDR *psHWTransferContextCpuVAddr, + IMG_UINT32 ui32HWTransferContextSize, + IMG_UINT32 ui32OffsetToPDDevPAddr, + IMG_HANDLE hDevMemContext, + IMG_DEV_VIRTADDR *psHWTransferContextDevVAddr, PVRSRV_PER_PROCESS_DATA *psPerProc) { PVRSRV_ERROR eError; IMG_HANDLE hBlockAlloc; SGX_HW_TRANSFER_CONTEXT_CLEANUP *psCleanup; + PVRSRV_DEVICE_NODE *psDeviceNode = (PVRSRV_DEVICE_NODE *)hDeviceNode; + DEVICE_MEMORY_INFO *psDevMemoryInfo; + DEVICE_MEMORY_HEAP_INFO *psHeapInfo; + IMG_HANDLE hDevMemContextInt; + MMU_CONTEXT *psMMUContext; + IMG_DEV_PHYADDR sPDDevPAddr; + int iPtrByte; + IMG_UINT8 *pSrc; + IMG_UINT8 *pDst; PRESMAN_ITEM psResItem; eError = OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP, @@ -872,12 +1005,99 @@ IMG_HANDLE SGXRegisterHWTransferContextKM(IMG_HANDLE psDeviceNode, if (eError != PVRSRV_OK) { PVR_DPF((PVR_DBG_ERROR, "SGXRegisterHWTransferContextKM: Couldn't allocate memory for SGX_HW_TRANSFER_CONTEXT_CLEANUP structure")); - return IMG_NULL; + goto exit0; + } + + psDevMemoryInfo = &psDeviceNode->sDevMemoryInfo; + psHeapInfo = &psDevMemoryInfo->psDeviceMemoryHeap[SGX_KERNEL_DATA_HEAP_ID]; + + eError = PVRSRVAllocDeviceMemKM(hDeviceNode, + psPerProc, + psHeapInfo->hDevMemHeap, + PVRSRV_MEM_READ | PVRSRV_MEM_WRITE + | PVRSRV_MEM_NO_SYNCOBJ | PVRSRV_MEM_EDM_PROTECT + | PVRSRV_MEM_CACHE_CONSISTENT, + ui32HWTransferContextSize, + 32, + IMG_NULL, + 0, + &psCleanup->psHWTransferContextMemInfo, + "HW Render Context"); + + if (eError != PVRSRV_OK) + { + PVR_DPF((PVR_DBG_ERROR, "SGXRegisterHWTransferContextKM: Couldn't allocate device memory for HW Render Context")); + goto exit1; + } + + eError = OSCopyFromUser(psPerProc, + psCleanup->psHWTransferContextMemInfo->pvLinAddrKM, + psHWTransferContextCpuVAddr, + ui32HWTransferContextSize); + + if (eError != PVRSRV_OK) + { + PVR_DPF((PVR_DBG_ERROR, "SGXRegisterHWTransferContextKM: Couldn't copy user-mode copy of HWContext into device memory")); + goto exit2; } + + psHWTransferContextDevVAddr->uiAddr = psCleanup->psHWTransferContextMemInfo->sDevVAddr.uiAddr; + + + eError = PVRSRVLookupHandle(psPerProc->psHandleBase, + &hDevMemContextInt, + hDevMemContext, + PVRSRV_HANDLE_TYPE_DEV_MEM_CONTEXT); + + if (eError != PVRSRV_OK) + { + PVR_DPF((PVR_DBG_ERROR, "SGXRegisterHWTransferContextKM: Can't lookup DevMem Context")); + goto exit2; + } + + psMMUContext = BM_GetMMUContextFromMemContext(hDevMemContextInt); + sPDDevPAddr = psDeviceNode->pfnMMUGetPDDevPAddr(psMMUContext); + + + + + + + pSrc = (IMG_UINT8 *)&sPDDevPAddr; + pDst = (IMG_UINT8 *)psCleanup->psHWTransferContextMemInfo->pvLinAddrKM; + pDst += ui32OffsetToPDDevPAddr; + + for (iPtrByte = 0; iPtrByte < sizeof(IMG_DEV_PHYADDR); iPtrByte++) + { + pDst[iPtrByte] = pSrc[iPtrByte]; + } + +#if defined(PDUMP) + + PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_CONTINUOUS, "HW Transfer context struct"); + + PDUMPMEM( + IMG_NULL, + psCleanup->psHWTransferContextMemInfo, + 0, + ui32HWTransferContextSize, + PDUMP_FLAGS_CONTINUOUS, + MAKEUNIQUETAG(psCleanup->psHWTransferContextMemInfo)); + + + PDUMPCOMMENT("Page directory address in HW transfer context"); + + PDUMPPDDEVPADDR( + psCleanup->psHWTransferContextMemInfo, + ui32OffsetToPDDevPAddr, + sPDDevPAddr, + MAKEUNIQUETAG(psCleanup->psHWTransferContextMemInfo), + PDUMP_PD_UNIQUETAG); +#endif + psCleanup->hBlockAlloc = hBlockAlloc; psCleanup->psDeviceNode = psDeviceNode; - psCleanup->sHWTransferContextDevVAddr = *psHWTransferContextDevVAddr; psResItem = ResManRegisterRes(psPerProc->hResManContext, RESMAN_TYPE_HW_TRANSFER_CONTEXT, @@ -888,18 +1108,25 @@ IMG_HANDLE SGXRegisterHWTransferContextKM(IMG_HANDLE psDeviceNode, if (psResItem == IMG_NULL) { PVR_DPF((PVR_DBG_ERROR, "SGXRegisterHWTransferContextKM: ResManRegisterRes failed")); - OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, - sizeof(SGX_HW_TRANSFER_CONTEXT_CLEANUP), - psCleanup, - psCleanup->hBlockAlloc); - - - return IMG_NULL; - } + goto exit2; + } psCleanup->psResItem = psResItem; return (IMG_HANDLE)psCleanup; + +exit2: + PVRSRVFreeDeviceMemKM(hDeviceNode, + psCleanup->psHWTransferContextMemInfo); +exit1: + OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, + sizeof(SGX_HW_TRANSFER_CONTEXT_CLEANUP), + psCleanup, + psCleanup->hBlockAlloc); + + +exit0: + return IMG_NULL; } IMG_EXPORT @@ -923,11 +1150,95 @@ PVRSRV_ERROR SGXUnregisterHWTransferContextKM(IMG_HANDLE hHWTransferContext, IMG return eError; } +IMG_EXPORT +PVRSRV_ERROR SGXSetTransferContextPriorityKM( + IMG_HANDLE hDeviceNode, + IMG_HANDLE hHWTransferContext, + IMG_UINT32 ui32Priority, + IMG_UINT32 ui32OffsetOfPriorityField) +{ + SGX_HW_TRANSFER_CONTEXT_CLEANUP *psCleanup; + IMG_UINT8 *pSrc; + IMG_UINT8 *pDst; + int iPtrByte; + PVR_UNREFERENCED_PARAMETER(hDeviceNode); + + if (hHWTransferContext != IMG_NULL) + { + psCleanup = (SGX_HW_TRANSFER_CONTEXT_CLEANUP *)hHWTransferContext; + + if ((ui32OffsetOfPriorityField + sizeof(ui32Priority)) + >= psCleanup->psHWTransferContextMemInfo->uAllocSize) + { + PVR_DPF(( + PVR_DBG_ERROR, + "SGXSetTransferContextPriorityKM: invalid context prioirty offset")); + + return PVRSRV_ERROR_INVALID_PARAMS; + } + + + + + pDst = (IMG_UINT8 *)psCleanup->psHWTransferContextMemInfo->pvLinAddrKM; + pDst += ui32OffsetOfPriorityField; + pSrc = (IMG_UINT8 *)&ui32Priority; + + for (iPtrByte = 0; iPtrByte < sizeof(ui32Priority); iPtrByte++) + { + pDst[iPtrByte] = pSrc[iPtrByte]; + } + } + return PVRSRV_OK; +} + +IMG_EXPORT +PVRSRV_ERROR SGXSetRenderContextPriorityKM( + IMG_HANDLE hDeviceNode, + IMG_HANDLE hHWRenderContext, + IMG_UINT32 ui32Priority, + IMG_UINT32 ui32OffsetOfPriorityField) +{ + SGX_HW_RENDER_CONTEXT_CLEANUP *psCleanup; + IMG_UINT8 *pSrc; + IMG_UINT8 *pDst; + int iPtrByte; + PVR_UNREFERENCED_PARAMETER(hDeviceNode); + + if (hHWRenderContext != IMG_NULL) + { + psCleanup = (SGX_HW_RENDER_CONTEXT_CLEANUP *)hHWRenderContext; + if ((ui32OffsetOfPriorityField + sizeof(ui32Priority)) + >= psCleanup->psHWRenderContextMemInfo->uAllocSize) + { + PVR_DPF(( + PVR_DBG_ERROR, + "SGXSetContextPriorityKM: invalid HWRenderContext prioirty offset")); + + return PVRSRV_ERROR_INVALID_PARAMS; + } + + + + + pDst = (IMG_UINT8 *)psCleanup->psHWRenderContextMemInfo->pvLinAddrKM; + pDst += ui32OffsetOfPriorityField; + + pSrc = (IMG_UINT8 *)&ui32Priority; + + for (iPtrByte = 0; iPtrByte < sizeof(ui32Priority); iPtrByte++) + { + pDst[iPtrByte] = pSrc[iPtrByte]; + } + } + return PVRSRV_OK; +} + #if defined(SGX_FEATURE_2D_HARDWARE) typedef struct _SGX_HW_2D_CONTEXT_CLEANUP_ { PVRSRV_DEVICE_NODE *psDeviceNode; - IMG_DEV_VIRTADDR sHW2DContextDevVAddr; + PVRSRV_KERNEL_MEM_INFO *psHW2DContextMemInfo; IMG_HANDLE hBlockAlloc; PRESMAN_ITEM psResItem; } SGX_HW_2D_CONTEXT_CLEANUP; @@ -941,28 +1252,46 @@ static PVRSRV_ERROR SGXCleanupHW2DContextCallback(IMG_PVOID pvParam, PVR_UNREFERENCED_PARAMETER(ui32Param); - eError = SGXCleanupRequest(psCleanup->psDeviceNode, - &psCleanup->sHW2DContextDevVAddr, + + eError = SGXCleanupRequest(psCleanup->psDeviceNode, + &psCleanup->psHW2DContextMemInfo->sDevVAddr, PVRSRV_CLEANUPCMD_2DC, bForceCleanup); - OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, + + PVRSRVFreeDeviceMemKM(psCleanup->psDeviceNode, + psCleanup->psHW2DContextMemInfo); + + + OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, sizeof(SGX_HW_2D_CONTEXT_CLEANUP), psCleanup, psCleanup->hBlockAlloc); - + return eError; } -IMG_EXPORT -IMG_HANDLE SGXRegisterHW2DContextKM(IMG_HANDLE psDeviceNode, - IMG_DEV_VIRTADDR *psHW2DContextDevVAddr, +IMG_HANDLE SGXRegisterHW2DContextKM(IMG_HANDLE hDeviceNode, + IMG_CPU_VIRTADDR *psHW2DContextCpuVAddr, + IMG_UINT32 ui32HW2DContextSize, + IMG_UINT32 ui32OffsetToPDDevPAddr, + IMG_HANDLE hDevMemContext, + IMG_DEV_VIRTADDR *psHW2DContextDevVAddr, PVRSRV_PER_PROCESS_DATA *psPerProc) { PVRSRV_ERROR eError; IMG_HANDLE hBlockAlloc; SGX_HW_2D_CONTEXT_CLEANUP *psCleanup; + PVRSRV_DEVICE_NODE *psDeviceNode = (PVRSRV_DEVICE_NODE *)hDeviceNode; + DEVICE_MEMORY_INFO *psDevMemoryInfo; + DEVICE_MEMORY_HEAP_INFO *psHeapInfo; + IMG_HANDLE hDevMemContextInt; + MMU_CONTEXT *psMMUContext; + IMG_DEV_PHYADDR sPDDevPAddr; + int iPtrByte; + IMG_UINT8 *pSrc; + IMG_UINT8 *pDst; PRESMAN_ITEM psResItem; eError = OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP, @@ -974,12 +1303,97 @@ IMG_HANDLE SGXRegisterHW2DContextKM(IMG_HANDLE psDeviceNode, if (eError != PVRSRV_OK) { PVR_DPF((PVR_DBG_ERROR, "SGXRegisterHW2DContextKM: Couldn't allocate memory for SGX_HW_2D_CONTEXT_CLEANUP structure")); - return IMG_NULL; + goto exit0; } + psDevMemoryInfo = &psDeviceNode->sDevMemoryInfo; + psHeapInfo = &psDevMemoryInfo->psDeviceMemoryHeap[SGX_KERNEL_DATA_HEAP_ID]; + + eError = PVRSRVAllocDeviceMemKM(hDeviceNode, + psPerProc, + psHeapInfo->hDevMemHeap, + PVRSRV_MEM_READ | PVRSRV_MEM_WRITE + | PVRSRV_MEM_NO_SYNCOBJ | PVRSRV_MEM_EDM_PROTECT + | PVRSRV_MEM_CACHE_CONSISTENT, + ui32HW2DContextSize, + 32, + IMG_NULL, + 0, + &psCleanup->psHW2DContextMemInfo, + "HW 2D Context"); + + if (eError != PVRSRV_OK) + { + PVR_DPF((PVR_DBG_ERROR, "SGXRegisterHW2DContextKM: Couldn't allocate device memory for HW Render Context")); + goto exit1; + } + + eError = OSCopyFromUser(psPerProc, + psCleanup->psHW2DContextMemInfo->pvLinAddrKM, + psHW2DContextCpuVAddr, + ui32HW2DContextSize); + if (eError != PVRSRV_OK) + { + PVR_DPF((PVR_DBG_ERROR, "SGXRegisterHW2DContextKM: Couldn't copy user-mode copy of HWContext into device memory")); + goto exit2; + } + + + psHW2DContextDevVAddr->uiAddr = psCleanup->psHW2DContextMemInfo->sDevVAddr.uiAddr; + + + eError = PVRSRVLookupHandle(psPerProc->psHandleBase, + &hDevMemContextInt, + hDevMemContext, + PVRSRV_HANDLE_TYPE_DEV_MEM_CONTEXT); + + if (eError != PVRSRV_OK) + { + PVR_DPF((PVR_DBG_ERROR, "SGXRegisterHW2DContextKM: Can't lookup DevMem Context")); + goto exit2; + } + + psMMUContext = BM_GetMMUContextFromMemContext(hDevMemContextInt); + sPDDevPAddr = psDeviceNode->pfnMMUGetPDDevPAddr(psMMUContext); + + + + + + + pSrc = (IMG_UINT8 *)&sPDDevPAddr; + pDst = (IMG_UINT8 *)psCleanup->psHW2DContextMemInfo->pvLinAddrKM; + pDst += ui32OffsetToPDDevPAddr; + + for (iPtrByte = 0; iPtrByte < sizeof(IMG_DEV_PHYADDR); iPtrByte++) + { + pDst[iPtrByte] = pSrc[iPtrByte]; + } + +#if defined(PDUMP) + + PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_CONTINUOUS, "HW 2D context struct"); + + PDUMPMEM( + IMG_NULL, + psCleanup->psHW2DContextMemInfo, + 0, + ui32HW2DContextSize, + PDUMP_FLAGS_CONTINUOUS, + MAKEUNIQUETAG(psCleanup->psHW2DContextMemInfo)); + + + PDUMPCOMMENT("Page directory address in HW 2D transfer context"); + PDUMPPDDEVPADDR( + psCleanup->psHW2DContextMemInfo, + ui32OffsetToPDDevPAddr, + sPDDevPAddr, + MAKEUNIQUETAG(psCleanup->psHW2DContextMemInfo), + PDUMP_PD_UNIQUETAG); +#endif + psCleanup->hBlockAlloc = hBlockAlloc; psCleanup->psDeviceNode = psDeviceNode; - psCleanup->sHW2DContextDevVAddr = *psHW2DContextDevVAddr; psResItem = ResManRegisterRes(psPerProc->hResManContext, RESMAN_TYPE_HW_2D_CONTEXT, @@ -990,18 +1404,24 @@ IMG_HANDLE SGXRegisterHW2DContextKM(IMG_HANDLE psDeviceNode, if (psResItem == IMG_NULL) { PVR_DPF((PVR_DBG_ERROR, "SGXRegisterHW2DContextKM: ResManRegisterRes failed")); - OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, - sizeof(SGX_HW_2D_CONTEXT_CLEANUP), - psCleanup, - psCleanup->hBlockAlloc); - - - return IMG_NULL; + goto exit2; } psCleanup->psResItem = psResItem; return (IMG_HANDLE)psCleanup; + +exit2: + PVRSRVFreeDeviceMemKM(hDeviceNode, + psCleanup->psHW2DContextMemInfo); +exit1: + OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, + sizeof(SGX_HW_2D_CONTEXT_CLEANUP), + psCleanup, + psCleanup->hBlockAlloc); + +exit0: + return IMG_NULL; } IMG_EXPORT @@ -1142,6 +1562,15 @@ IMG_UINT32 SGXConvertTimeStamp(PVRSRV_SGXDEV_INFO *psDevInfo, } +IMG_VOID SGXWaitClocks(PVRSRV_SGXDEV_INFO *psDevInfo, + IMG_UINT32 ui32SGXClocks) +{ + + + OSWaitus(1 + (ui32SGXClocks * 1000000 / psDevInfo->ui32CoreClockSpeed)); +} + + IMG_EXPORT PVRSRV_ERROR PVRSRVGetSGXRevDataKM(PVRSRV_DEVICE_NODE* psDeviceNode, IMG_UINT32 *pui32SGXCoreRev, diff --git a/drivers/gpu/pvr/sgx/sgxutils.h b/drivers/gpu/pvr/sgx/sgxutils.h index bc60fdd..ae6dbc7 100644 --- a/drivers/gpu/pvr/sgx/sgxutils.h +++ b/drivers/gpu/pvr/sgx/sgxutils.h @@ -66,13 +66,21 @@ IMG_BOOL SGXIsDevicePowered(PVRSRV_DEVICE_NODE *psDeviceNode); IMG_IMPORT IMG_HANDLE SGXRegisterHWRenderContextKM(IMG_HANDLE psDeviceNode, - IMG_DEV_VIRTADDR *psHWRenderContextDevVAddr, + IMG_CPU_VIRTADDR *psHWRenderContextCpuVAddr, + IMG_UINT32 ui32HWRenderContextSize, + IMG_UINT32 ui32OffsetToPDDevPAddr, + IMG_HANDLE hDevMemContext, + IMG_DEV_VIRTADDR *psHWRenderContextDevVAddr, PVRSRV_PER_PROCESS_DATA *psPerProc); IMG_IMPORT -IMG_HANDLE SGXRegisterHWTransferContextKM(IMG_HANDLE psDeviceNode, - IMG_DEV_VIRTADDR *psHWTransferContextDevVAddr, - PVRSRV_PER_PROCESS_DATA *psPerProc); +IMG_HANDLE SGXRegisterHWTransferContextKM(IMG_HANDLE psDeviceNode, + IMG_CPU_VIRTADDR *psHWTransferContextCpuVAddr, + IMG_UINT32 ui32HWTransferContextSize, + IMG_UINT32 ui32OffsetToPDDevPAddr, + IMG_HANDLE hDevMemContext, + IMG_DEV_VIRTADDR *psHWTransferContextDevVAddr, + PVRSRV_PER_PROCESS_DATA *psPerProc); IMG_IMPORT PVRSRV_ERROR SGXFlushHWRenderTargetKM(IMG_HANDLE psSGXDevInfo, @@ -85,10 +93,26 @@ PVRSRV_ERROR SGXUnregisterHWRenderContextKM(IMG_HANDLE hHWRenderContext, IMG_BOO IMG_IMPORT PVRSRV_ERROR SGXUnregisterHWTransferContextKM(IMG_HANDLE hHWTransferContext, IMG_BOOL bForceCleanup); +IMG_IMPORT +PVRSRV_ERROR SGXSetRenderContextPriorityKM(IMG_HANDLE hDeviceNode, + IMG_HANDLE hHWRenderContext, + IMG_UINT32 ui32Priority, + IMG_UINT32 ui32OffsetOfPriorityField); + +IMG_IMPORT +PVRSRV_ERROR SGXSetTransferContextPriorityKM(IMG_HANDLE hDeviceNode, + IMG_HANDLE hHWTransferContext, + IMG_UINT32 ui32Priority, + IMG_UINT32 ui32OffsetOfPriorityField); + #if defined(SGX_FEATURE_2D_HARDWARE) IMG_IMPORT IMG_HANDLE SGXRegisterHW2DContextKM(IMG_HANDLE psDeviceNode, - IMG_DEV_VIRTADDR *psHW2DContextDevVAddr, + IMG_CPU_VIRTADDR *psHW2DContextCpuVAddr, + IMG_UINT32 ui32HW2DContextSize, + IMG_UINT32 ui32OffsetToPDDevPAddr, + IMG_HANDLE hDevMemContext, + IMG_DEV_VIRTADDR *psHW2DContextDevVAddr, PVRSRV_PER_PROCESS_DATA *psPerProc); IMG_IMPORT @@ -99,6 +123,9 @@ IMG_UINT32 SGXConvertTimeStamp(PVRSRV_SGXDEV_INFO *psDevInfo, IMG_UINT32 ui32TimeWraps, IMG_UINT32 ui32Time); +IMG_VOID SGXWaitClocks(PVRSRV_SGXDEV_INFO *psDevInfo, + IMG_UINT32 ui32SGXClocks); + PVRSRV_ERROR SGXCleanupRequest(PVRSRV_DEVICE_NODE *psDeviceNode, IMG_DEV_VIRTADDR *psHWDataDevVAddr, IMG_UINT32 ui32CleanupType, diff --git a/drivers/gpu/pvr/sgx_bridge.h b/drivers/gpu/pvr/sgx_bridge.h index 204189c..ec630a5 100644 --- a/drivers/gpu/pvr/sgx_bridge.h +++ b/drivers/gpu/pvr/sgx_bridge.h @@ -50,8 +50,6 @@ extern "C" { #define PVRSRV_BRIDGE_SGX_2DQUERYBLTSCOMPLETE PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+9) -#define PVRSRV_BRIDGE_SGX_GETMMUPDADDR PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+10) - #if defined(TRANSFER_QUEUE) #define PVRSRV_BRIDGE_SGX_SUBMITTRANSFER PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+13) #endif @@ -75,20 +73,22 @@ extern "C" { #define PVRSRV_BRIDGE_SGX_SCHEDULE_PROCESS_QUEUES PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+28) -#define PVRSRV_BRIDGE_SGX_READ_HWPERF_CB PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+30) +#define PVRSRV_BRIDGE_SGX_READ_HWPERF_CB PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+29) +#define PVRSRV_BRIDGE_SGX_SET_RENDER_CONTEXT_PRIORITY PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+30) +#define PVRSRV_BRIDGE_SGX_SET_TRANSFER_CONTEXT_PRIORITY PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+31) #if defined(PDUMP) -#define PVRSRV_BRIDGE_SGX_PDUMP_BUFFER_ARRAY PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+31) -#define PVRSRV_BRIDGE_SGX_PDUMP_3D_SIGNATURE_REGISTERS PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+32) -#define PVRSRV_BRIDGE_SGX_PDUMP_COUNTER_REGISTERS PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+33) -#define PVRSRV_BRIDGE_SGX_PDUMP_TA_SIGNATURE_REGISTERS PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+34) -#define PVRSRV_BRIDGE_SGX_PDUMP_HWPERFCB PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+35) -#define PVRSRV_BRIDGE_SGX_PDUMP_SAVEMEM PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+36) +#define PVRSRV_BRIDGE_SGX_PDUMP_BUFFER_ARRAY PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+32) +#define PVRSRV_BRIDGE_SGX_PDUMP_3D_SIGNATURE_REGISTERS PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+33) +#define PVRSRV_BRIDGE_SGX_PDUMP_COUNTER_REGISTERS PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+34) +#define PVRSRV_BRIDGE_SGX_PDUMP_TA_SIGNATURE_REGISTERS PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+35) +#define PVRSRV_BRIDGE_SGX_PDUMP_HWPERFCB PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+36) +#define PVRSRV_BRIDGE_SGX_PDUMP_SAVEMEM PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+37) #endif -#define PVRSRV_BRIDGE_LAST_SGX_CMD (PVRSRV_BRIDGE_SGX_CMD_BASE+36) +#define PVRSRV_BRIDGE_LAST_SGX_CMD (PVRSRV_BRIDGE_SGX_CMD_BASE+37) typedef struct PVRSRV_BRIDGE_IN_GETPHYSPAGEADDR @@ -107,24 +107,34 @@ typedef struct PVRSRV_BRIDGE_OUT_GETPHYSPAGEADDR }PVRSRV_BRIDGE_OUT_GETPHYSPAGEADDR; -typedef struct PVRSRV_BRIDGE_IN_SGX_GETMMU_PDADDR_TAG +typedef struct PVRSRV_BRIDGE_IN_SGX_SET_TRANSFER_CONTEXT_PRIORITY_TAG + { + IMG_UINT32 ui32BridgeFlags; + #if defined (SUPPORT_SID_INTERFACE) + IMG_SID hDevCookie; + IMG_SID hHWTransferContext; + #else + IMG_HANDLE hDevCookie; + IMG_HANDLE hHWTransferContext; + #endif + IMG_UINT32 ui32Priority; + IMG_UINT32 ui32OffsetOfPriorityField; +}PVRSRV_BRIDGE_IN_SGX_SET_TRANSFER_CONTEXT_PRIORITY; + + +typedef struct PVRSRV_BRIDGE_IN_SGX_SET_RENDER_CONTEXT_PRIORITY_TAG { IMG_UINT32 ui32BridgeFlags; #if defined (SUPPORT_SID_INTERFACE) IMG_SID hDevCookie; - IMG_SID hDevMemContext; + IMG_SID hHWRenderContext; #else IMG_HANDLE hDevCookie; - IMG_HANDLE hDevMemContext; + IMG_HANDLE hHWRenderContext; #endif -}PVRSRV_BRIDGE_IN_SGX_GETMMU_PDADDR; - - -typedef struct PVRSRV_BRIDGE_OUT_SGX_GETMMU_PDADDR_TAG -{ - IMG_DEV_PHYADDR sPDDevPAddr; - PVRSRV_ERROR eError; -}PVRSRV_BRIDGE_OUT_SGX_GETMMU_PDADDR; + IMG_UINT32 ui32Priority; + IMG_UINT32 ui32OffsetOfPriorityField; +}PVRSRV_BRIDGE_IN_SGX_SET_RENDER_CONTEXT_PRIORITY; typedef struct PVRSRV_BRIDGE_IN_GETCLIENTINFO_TAG @@ -505,7 +515,10 @@ typedef struct PVRSRV_BRIDGE_IN_SGX_REGISTER_HW_RENDER_CONTEXT_TAG #else IMG_HANDLE hDevCookie; #endif - IMG_DEV_VIRTADDR sHWRenderContextDevVAddr; + IMG_CPU_VIRTADDR pHWRenderContextCpuVAddr; + IMG_UINT32 ui32HWRenderContextSize; + IMG_UINT32 ui32OffsetToPDDevPAddr; + IMG_HANDLE hDevMemContext; }PVRSRV_BRIDGE_IN_SGX_REGISTER_HW_RENDER_CONTEXT; typedef struct PVRSRV_BRIDGE_OUT_SGX_REGISTER_HW_RENDER_CONTEXT_TAG @@ -516,6 +529,7 @@ typedef struct PVRSRV_BRIDGE_OUT_SGX_REGISTER_HW_RENDER_CONTEXT_TAG #else IMG_HANDLE hHWRenderContext; #endif + IMG_DEV_VIRTADDR sHWRenderContextDevVAddr; }PVRSRV_BRIDGE_OUT_SGX_REGISTER_HW_RENDER_CONTEXT; typedef struct PVRSRV_BRIDGE_IN_SGX_UNREGISTER_HW_RENDER_CONTEXT_TAG @@ -539,7 +553,10 @@ typedef struct PVRSRV_BRIDGE_IN_SGX_REGISTER_HW_TRANSFER_CONTEXT_TAG #else IMG_HANDLE hDevCookie; #endif - IMG_DEV_VIRTADDR sHWTransferContextDevVAddr; + IMG_CPU_VIRTADDR pHWTransferContextCpuVAddr; + IMG_UINT32 ui32HWTransferContextSize; + IMG_UINT32 ui32OffsetToPDDevPAddr; + IMG_HANDLE hDevMemContext; }PVRSRV_BRIDGE_IN_SGX_REGISTER_HW_TRANSFER_CONTEXT; typedef struct PVRSRV_BRIDGE_OUT_SGX_REGISTER_HW_TRANSFER_CONTEXT_TAG @@ -550,6 +567,7 @@ typedef struct PVRSRV_BRIDGE_OUT_SGX_REGISTER_HW_TRANSFER_CONTEXT_TAG #else IMG_HANDLE hHWTransferContext; #endif + IMG_DEV_VIRTADDR sHWTransferContextDevVAddr; }PVRSRV_BRIDGE_OUT_SGX_REGISTER_HW_TRANSFER_CONTEXT; typedef struct PVRSRV_BRIDGE_IN_SGX_UNREGISTER_HW_TRANSFER_CONTEXT_TAG @@ -586,7 +604,10 @@ typedef struct PVRSRV_BRIDGE_IN_SGX_REGISTER_HW_2D_CONTEXT_TAG #else IMG_HANDLE hDevCookie; #endif - IMG_DEV_VIRTADDR sHW2DContextDevVAddr; + IMG_CPU_VIRTADDR pHW2DContextCpuVAddr; + IMG_UINT32 ui32HW2DContextSize; + IMG_UINT32 ui32OffsetToPDDevPAddr; + IMG_HANDLE hDevMemContext; }PVRSRV_BRIDGE_IN_SGX_REGISTER_HW_2D_CONTEXT; typedef struct PVRSRV_BRIDGE_OUT_SGX_REGISTER_HW_2D_CONTEXT_TAG @@ -597,6 +618,7 @@ typedef struct PVRSRV_BRIDGE_OUT_SGX_REGISTER_HW_2D_CONTEXT_TAG #else IMG_HANDLE hHW2DContext; #endif + IMG_DEV_VIRTADDR sHW2DContextDevVAddr; }PVRSRV_BRIDGE_OUT_SGX_REGISTER_HW_2D_CONTEXT; typedef struct PVRSRV_BRIDGE_IN_SGX_UNREGISTER_HW_2D_CONTEXT_TAG diff --git a/drivers/gpu/pvr/sgxerrata.h b/drivers/gpu/pvr/sgxerrata.h index 8a3632f..81de9d2 100644 --- a/drivers/gpu/pvr/sgxerrata.h +++ b/drivers/gpu/pvr/sgxerrata.h @@ -548,9 +548,6 @@ #if SGX_CORE_REV == 106 #define FIX_HW_BRN_31272 #define FIX_HW_BRN_31780 - #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_33657 - #endif #define FIX_HW_BRN_33920 #else #if SGX_CORE_REV == 110 diff --git a/drivers/gpu/pvr/sgxfeaturedefs.h b/drivers/gpu/pvr/sgxfeaturedefs.h index cd761d6..3850e6b 100644 --- a/drivers/gpu/pvr/sgxfeaturedefs.h +++ b/drivers/gpu/pvr/sgxfeaturedefs.h @@ -28,18 +28,21 @@ #define SGX_CORE_FRIENDLY_NAME "SGX520" #define SGX_CORE_ID SGX_CORE_ID_520 #define SGX_FEATURE_ADDRESS_SPACE_SIZE (28) + #define SGX_FEATURE_NUM_USE_PIPES (1) #define SGX_FEATURE_AUTOCLOCKGATING #else #if defined(SGX530) #define SGX_CORE_FRIENDLY_NAME "SGX530" #define SGX_CORE_ID SGX_CORE_ID_530 #define SGX_FEATURE_ADDRESS_SPACE_SIZE (28) + #define SGX_FEATURE_NUM_USE_PIPES (2) #define SGX_FEATURE_AUTOCLOCKGATING #else #if defined(SGX531) #define SGX_CORE_FRIENDLY_NAME "SGX531" #define SGX_CORE_ID SGX_CORE_ID_531 #define SGX_FEATURE_ADDRESS_SPACE_SIZE (28) + #define SGX_FEATURE_NUM_USE_PIPES (2) #define SGX_FEATURE_AUTOCLOCKGATING #define SGX_FEATURE_MULTI_EVENT_KICK #else @@ -50,6 +53,7 @@ #define SGX_FEATURE_MULTIPLE_MEM_CONTEXTS #define SGX_FEATURE_BIF_NUM_DIRLISTS (16) #define SGX_FEATURE_2D_HARDWARE + #define SGX_FEATURE_NUM_USE_PIPES (2) #define SGX_FEATURE_AUTOCLOCKGATING #define SUPPORT_SGX_GENERAL_MAPPING_HEAP #define SGX_FEATURE_EDM_VERTEX_PDSADDR_FULL_RANGE @@ -58,6 +62,7 @@ #define SGX_CORE_FRIENDLY_NAME "SGX540" #define SGX_CORE_ID SGX_CORE_ID_540 #define SGX_FEATURE_ADDRESS_SPACE_SIZE (28) + #define SGX_FEATURE_NUM_USE_PIPES (4) #define SGX_FEATURE_AUTOCLOCKGATING #define SGX_FEATURE_MULTI_EVENT_KICK #else @@ -69,6 +74,7 @@ #define SGX_FEATURE_ADDRESS_SPACE_SIZE (32) #define SGX_FEATURE_MULTIPLE_MEM_CONTEXTS #define SGX_FEATURE_BIF_NUM_DIRLISTS (8) + #define SGX_FEATURE_NUM_USE_PIPES (4) #define SGX_FEATURE_AUTOCLOCKGATING #define SGX_FEATURE_MONOLITHIC_UKERNEL #define SGX_FEATURE_MULTI_EVENT_KICK @@ -95,15 +101,13 @@ #define SGX_FEATURE_ADDRESS_SPACE_SIZE (32) #define SGX_FEATURE_MULTIPLE_MEM_CONTEXTS #define SGX_FEATURE_BIF_NUM_DIRLISTS (8) + #define SGX_FEATURE_NUM_USE_PIPES (4) #define SGX_FEATURE_AUTOCLOCKGATING #define SGX_FEATURE_MONOLITHIC_UKERNEL #define SGX_FEATURE_MULTI_EVENT_KICK #define SGX_FEATURE_EXTENDED_PERF_COUNTERS #define SGX_FEATURE_EDM_VERTEX_PDSADDR_FULL_RANGE #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) - #if defined(SGX_FEATURE_MP) - #define SGX_FEATURE_MASTER_VDM_CONTEXT_SWITCH - #endif #define SGX_FEATURE_SW_VDM_CONTEXT_SWITCH #define SGX_FEATURE_SW_ISP_CONTEXT_SWITCH #endif @@ -146,6 +150,7 @@ #define SGX_FEATURE_ADDRESS_SPACE_SIZE (32) #define SGX_FEATURE_MULTIPLE_MEM_CONTEXTS #define SGX_FEATURE_BIF_NUM_DIRLISTS (8) + #define SGX_FEATURE_NUM_USE_PIPES (8) #define SGX_FEATURE_AUTOCLOCKGATING #define SGX_FEATURE_MONOLITHIC_UKERNEL #define SGX_FEATURE_MULTI_EVENT_KICK |