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| * ARM: orion: Fix USB phy for orion5x.Andrew Lunn2012-03-126-10/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 72053353583230952c4b187e110e9da00dfc3afb upstream. The patch "ARM: orion: Consolidate USB platform setup code.", commit 4fcd3f374a928081d391cd9a570afe3b2c692fdc broke USB on TS-7800 and other orion5x boards, because the wrong type of PHY was being passed to the EHCI driver in the platform data. Orion5x needs EHCI_PHY_ORION and all the others want EHCI_PHY_NA. Allow the mach- code to tell the generic plat-orion code which USB PHY enum to place into the platform data. Version 2: Rebase to v3.3-rc2. Reported-by: Ambroz Bizjak <ambrop7@gmail.com> Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Ambroz Bizjak <ambrop7@gmail.com> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * ARM: S3C24XX: DMA resume regression fixGusakov Andrey2012-03-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | commit e39d40c65dfd8390b50c03482ae9e289b8a8f351 upstream. s3c2410_dma_suspend suspends channels from 0 to dma_channels. s3c2410_dma_resume resumes channels in reverse order. So pointer should be decremented instead of being incremented. Signed-off-by: Gusakov Andrey <dron0gus@gmail.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * ARM: LPC32xx: Fix irq on GPI_28Roland Stigge2012-03-122-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | commit f6737055c1c432a9628a9a731f9881ad8e0a9eee upstream. The GPI_28 IRQ was not registered properly. The registration of IRQ_LPC32XX_GPI_28 was added and the (wrong) IRQ_LPC32XX_GPI_11 at LPC32XX_SIC1_IRQ(4) was replaced by IRQ_LPC32XX_GPI_28 (see manual of LPC32xx / interrupt controller). Signed-off-by: Roland Stigge <stigge@antcom.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * ARM: LPC32xx: Fix interrupt controller initRoland Stigge2012-03-121-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | commit 35dd0a75d4a382e7f769dd0277732e7aa5235718 upstream. This patch fixes the initialization of the interrupt controller of the LPC32xx by correctly setting up SIC1 and SIC2 instead of (wrongly) using the same value as for the Main Interrupt Controller (MIC). Signed-off-by: Roland Stigge <stigge@antcom.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * ARM: LPC32xx: irq.c: Clear latched eventRoland Stigge2012-03-121-1/+10
| | | | | | | | | | | | | | | | | | | | commit 94ed7830cba4dce57b18a2926b5d826bfd184bd6 upstream. This patch fixes the wakeup disable function by clearing latched events. Signed-off-by: Roland Stigge <stigge@antcom.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * ARM: LPC32xx: serial.c: Fixed loop limitRoland Stigge2012-03-121-1/+1
| | | | | | | | | | | | | | | | | | | | commit ff424aa4c89d19082e8ae5a3351006bc8a4cd91b upstream. This patch fixes a wrong loop limit on UART init. Signed-off-by: Roland Stigge <stigge@antcom.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * ARM: LPC32xx: serial.c: HW bug workaroundRoland Stigge2012-03-121-0/+18
| | | | | | | | | | | | | | | | | | | | | | commit 2707208ee8a80dbbd5426f5aa1a934f766825bb5 upstream. This patch fixes a HW bug by flushing RX FIFOs of the UARTs on init. It was ported from NXP's git.lpclinux.com tree. Signed-off-by: Roland Stigge <stigge@antcom.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * ARM: 7325/1: fix v7 boot with lockdep enabledRabin Vincent2012-02-292-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 8e43a905dd574f54c5715d978318290ceafbe275 upstream. Bootup with lockdep enabled has been broken on v7 since b46c0f74657d ("ARM: 7321/1: cache-v7: Disable preemption when reading CCSIDR"). This is because v7_setup (which is called very early during boot) calls v7_flush_dcache_all, and the save_and_disable_irqs added by that patch ends up attempting to call into lockdep C code (trace_hardirqs_off()) when we are in no position to execute it (no stack, MMU off). Fix this by using a notrace variant of save_and_disable_irqs. The code already uses the notrace variant of restore_irqs. Reviewed-by: Nicolas Pitre <nico@linaro.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Rabin Vincent <rabin@rab.in> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * ARM: 7321/1: cache-v7: Disable preemption when reading CCSIDRStephen Boyd2012-02-291-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit b46c0f74657d1fe1c1b0c1452631cc38a9e6987f upstream. armv7's flush_cache_all() flushes caches via set/way. To determine the cache attributes (line size, number of sets, etc.) the assembly first writes the CSSELR register to select a cache level and then reads the CCSIDR register. The CSSELR register is banked per-cpu and is used to determine which cache level CCSIDR reads. If the task is migrated between when the CSSELR is written and the CCSIDR is read the CCSIDR value may be for an unexpected cache level (for example L1 instead of L2) and incorrect cache flushing could occur. Disable interrupts across the write and read so that the correct cache attributes are read and used for the cache flushing routine. We disable interrupts instead of disabling preemption because the critical section is only 3 instructions and we want to call v7_dcache_flush_all from __v7_setup which doesn't have a full kernel stack with a struct thread_info. This fixes a problem we see in scm_call() when flush_cache_all() is called from preemptible context and sometimes the L2 cache is not properly flushed out. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | ARM: 7670/1: fix the memset fixNicolas Pitre2015-09-191-20/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 455bd4c430b0 ("ARM: 7668/1: fix memset-related crashes caused by recent GCC (4.7.2) optimizations") attempted to fix a compliance issue with the memset return value. However the memset itself became broken by that patch for misaligned pointers. This fixes the above by branching over the entry code from the misaligned fixup code to avoid reloading the original pointer. Also, because the function entry alignment is wrong in the Thumb mode compilation, that fixup code is moved to the end. While at it, the entry instructions are slightly reworked to help dual issue pipelines. Change-Id: I8f122b3130626039e90110faae6bad2cc8148df7 Signed-off-by: Nicolas Pitre <nico@linaro.org> Tested-by: Alexander Holler <holler@ahsoftware.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | ARM: 7668/1: fix memset-related crashes caused by recent GCC (4.7.2) ↵Ivan Djelic2015-09-191-41/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | optimizations Recent GCC versions (e.g. GCC-4.7.2) perform optimizations based on assumptions about the implementation of memset and similar functions. The current ARM optimized memset code does not return the value of its first argument, as is usually expected from standard implementations. For instance in the following function: void debug_mutex_lock_common(struct mutex *lock, struct mutex_waiter *waiter) { memset(waiter, MUTEX_DEBUG_INIT, sizeof(*waiter)); waiter->magic = waiter; INIT_LIST_HEAD(&waiter->list); } compiled as: 800554d0 <debug_mutex_lock_common>: 800554d0: e92d4008 push {r3, lr} 800554d4: e1a00001 mov r0, r1 800554d8: e3a02010 mov r2, #16 ; 0x10 800554dc: e3a01011 mov r1, #17 ; 0x11 800554e0: eb04426e bl 80165ea0 <memset> 800554e4: e1a03000 mov r3, r0 800554e8: e583000c str r0, [r3, #12] 800554ec: e5830000 str r0, [r3] 800554f0: e5830004 str r0, [r3, #4] 800554f4: e8bd8008 pop {r3, pc} GCC assumes memset returns the value of pointer 'waiter' in register r0; causing register/memory corruptions. This patch fixes the return value of the assembly version of memset. It adds a 'mov' instruction and merges an additional load+store into existing load/store instructions. For ease of review, here is a breakdown of the patch into 4 simple steps: Step 1 ====== Perform the following substitutions: ip -> r8, then r0 -> ip, and insert 'mov ip, r0' as the first statement of the function. At this point, we have a memset() implementation returning the proper result, but corrupting r8 on some paths (the ones that were using ip). Step 2 ====== Make sure r8 is saved and restored when (! CALGN(1)+0) == 1: save r8: - str lr, [sp, #-4]! + stmfd sp!, {r8, lr} and restore r8 on both exit paths: - ldmeqfd sp!, {pc} @ Now <64 bytes to go. + ldmeqfd sp!, {r8, pc} @ Now <64 bytes to go. (...) tst r2, #16 stmneia ip!, {r1, r3, r8, lr} - ldr lr, [sp], #4 + ldmfd sp!, {r8, lr} Step 3 ====== Make sure r8 is saved and restored when (! CALGN(1)+0) == 0: save r8: - stmfd sp!, {r4-r7, lr} + stmfd sp!, {r4-r8, lr} and restore r8 on both exit paths: bgt 3b - ldmeqfd sp!, {r4-r7, pc} + ldmeqfd sp!, {r4-r8, pc} (...) tst r2, #16 stmneia ip!, {r4-r7} - ldmfd sp!, {r4-r7, lr} + ldmfd sp!, {r4-r8, lr} Step 4 ====== Rewrite register list "r4-r7, r8" as "r4-r8". Change-Id: I68561de7228bcdc0e61ecbbcf023f42b9d1fb9f9 Signed-off-by: Ivan Djelic <ivan.djelic@parrot.com> Reviewed-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Dirk Behme <dirk.behme@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | OMAP4: board: power: Add Fuel Gauge configurationMax Herman2012-12-182-3/+85
| | | | | | | | | | Change-Id: I81b3865daee3241d34f9209888010e3ba1e8984e Signed-off-by: Max Herman <mherman@fsisys.com>
* | ARM: OMAP4: omap-twl: Fix setting VSEL code for max_voltageOleg_Kosheliev2012-12-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Errata ProDB00121179 says voltage overshoot may occur if switch from DVS to non-DVS ranges on TWL6032. - DVS range VSEL codes 0x01-0x39 - non-DVS range VSEL codes 0x3A-0x3E Max_volt settings (1.418V) were converted to VSEL=0x3A. This VSEL code is in non-DVS range while all other codes are in DVS range. Thus using this code leads to voltage overshoot due to errata. Now max_volt 1.418V is converted to code VSEL=0x39 which corresponds to 1.417960V and is in the safe range. The voltages higher than 1.418V aren't used for both 6030 and 6032. Thus replacing VSEL code 0x3A by 0x39 does not impact performance. If used SMPS_OFFSET=0 (default only for twl6030 es1.0 and is not used on twl6032) the max voltage of 1.35V is recalculated to VSEL=0x3A and is not affected by the patch. Change-Id: I5e992be09899f520c1635fe3c268cbfdedc4caf4 Signed-off-by: Oleg_Kosheliev <oleg.kosheliev@ti.com>
* | OMAP4: EMIF: LPDDR interface configuration updateRuslan Bilovol2012-11-272-6/+24
| | | | | | | | | | | | | | | | | | In latest TRMs for OMAP4 family LPDDR recommended setting have been changed. This patch does corresponding changes in the code. Change-Id: Ibd81b8196db74df5a7c3e29788c72a7b3628a22c Signed-off-by: Ruslan Bilovol <ruslan.bilovol@ti.com>
* | OMAP4430/60: EMIF: errata: Prohibit usage of Power-Down modeGrygorii Strashko2012-11-201-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A ZQ calibration long command is issued every time on exit from active power-down and precharge power-down modes when EMIF is configured to use Power-down mode (EMIF_PWR_MGMT_CTRL.REG_LP_MODE=0x4). Due to very short periods of power-down cycles, ZQ calibration overhead creates bandwidth issues and increases overall system power consumption. As result, the guideline is to not allow Power-down mode and, therefore, to not have set the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field to 0x4. TI Errata i743; IMPACTED: OMAP4430/60 all revisions Change-Id: Ib82f28e6e0c6c046ea277b90a78dc82c1ee82417 Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Vitaly Chernooky <vitaly.chernooky@ti.com>
* | OMAP4: DPLL cascading: remove unused CM_SHADOW_FREQ_CONFIG2Eugen Mandrenko2012-11-151-42/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The value from CM_SHADOW_FREQ_CONFIG2 can't be applied because GPMC is always active and can't be entered in idle state. The GPMC is always active because on OMAP4, CPU accesses on unmapped addresses are redirected to GPMC by L3 interconnect. CPU is speculative nature and such accesses are possible which can lead to indirect access to GPMC and if it's clock is not running, it can result in hang/abort on the platform. See path d60565948468b for more information. Change-Id: Ia62d8bf8c59ac3a06445b6f5f9e08ad0c9369c5b Signed-off-by: Eugen Mandrenko <ievgen.mandrenko@ti.com>
* | OMAP4: EMIF: code cleanup and clarificationRuslan Bilovol2012-11-152-165/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Removed unused fields of emif_regs structure and functions that initialize or change them. Also changed few names of emif_regs members to match register names. This made the code easier to understand and read as well as made it a little bit faster Change-Id: I0485a01b7f03e922b5a2e69bfb03c2ed941fcf3b Signed-off-by: Ruslan Bilovol <ruslan.bilovol@ti.com>
* | Tablet2: tc358765: Brightness should not affect gpio 102Andrii Anisov2012-11-071-13/+1
| | | | | | | | | | | | | | | | | | | | | | | | Gpio 102 is shared between two functionalities: resetting tc358765 and backlight enabling. This leads to unwanted tc358765 reset if backlight is set to 0 from user space. To avoid this situation handling gpio 102 is removed from backlight control. Theoretically backlight should be sufficiently controlled with PWM and a separate enable pin handling is not mandatory Change-Id: Ic7e3a4799cbc966238c7086dd2500d2e2ed0b851 Signed-off-by: Andrii Anisov <andrii.anisov@ti.com>
* | blaze_defconfig: build gps driver as modulesBindu2012-11-061-0/+1
| | | | | | | | | | | | | | TI's GPS solution for Android expects gps driver to be built as a module. Change-Id: If7d989c74363ab719f08c308e7c746fd4cf8d324 Signed-off-by: Bindu <bkurian@ti.com>
* | OMAP4: DPLL cascading: exit cascading before system restartVolodymyr Mieshkov2012-11-061-0/+9
| | | | | | | | | | | | | | | | | | | | | | Exiting from DPLL cascading on system restart should be done before CPUs are turned off. In other case deadlocks are possible when mutex locked with idled CPU could be acquired with an active CPU. Change-Id: I608f8aee6c6f3e9a2c1fca0f06ea836222b121c2 Signed-off-by: Taras Kondratiuk <taras@ti.com> Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com> Signed-off-by: Volodymyr Mieshkov <volodymyr.mieshkov@ti.com>
* | Revert "OMAP4: DPLL cascading: hold DPLL cascading constraint before warm reset"Volodymyr Mieshkov2012-11-061-11/+0
| | | | | | | | | | | | | | | | | | | | This reverts commit effa7fbff1abfea9be9d2aa886a794c1f3aefe69. Exiting from DPLL cascading on system restart should be done before CPUs are turned off. Change-Id: I9e8bdc777daee71bf3c5963a3b95fb627153f13b Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com> Signed-off-by: Volodymyr Mieshkov <volodymyr.mieshkov@ti.com>
* | ARM: OMAP4: trim_quirks: Repair the wrong comparisonIvan Khoronzhuk2012-11-061-1/+1
| | | | | | | | | | | | | | The omap_rev() returns value not comparable with CHIP_IS_* constants. Change-Id: I4f21fc84b37f09d1c14c2656bf13337a453d783e Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* | OMAP4: Tablet2: configure TC35876x panel refresh rate to 60 fpsSergiy Kibrik2012-10-301-6/+46
| | | | | | | | | | | | | | | | Current configuration refreshes the LCD at ~70 fps, which is more than UI expects and also can impact power consumption. This is now corercted to 60 fps. Change-Id: I98ce97b35f0458b1e24040fe0556aa698b3b00a2 Signed-off-by: Sergiy Kibrik <sergiy.kibrik@globallogic.com>
* | OMAP: process tput request made before PM init.John Grossman2012-10-266-14/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | Because driver load order is uncertain, drivers could request bus throughput constraints before the PM subsystem had initialized. The constraints would be recorded, but would have no effect on the actual L3 clock. This change suppresses attempts to set L3 scaling before PM has initialized, and causes the PM subsystem to apply any pending bus throughput constraints immediately after it has initialized itself. Change-Id: If2a1f5315b8c1b084e4e4b3ce8e6844d92dd59b6 Signed-off-by: John Grossman <johngro@google.com> Signed-off-by: Ruslan Bilovol <ruslan.bilovol@ti.com>
* | OMAP4: Tablet: Set invalid reset_gpio for HDMIAndrii Anisov2012-10-251-0/+1
| | | | | | | | | | | | | | | | Set invalid reset_gpio for HDMI default display platform data, in order to not get any gpio requested. Change-Id: I544156780ec9eace39651f042558e7eab0dda619 Signed-off-by: Andrii Anisov <andrii.anisov@ti.com>
* | omap: ion: increase ducati memory from 107MB to 109MBJuan Gutierrez2012-10-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The carveout size required for the ducati firmware image has been increased by 2MB to allow an increased external data size on the remote processor side. This change is automatically reflected for OMAP4 Blaze, Tablet and Panda boards. Change-Id: I1b3d6e77360df1b82d670b003053b7086d168461 Signed-off-by: Juan Gutierrez <jgutierrez@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com>
* | ARM: backtrace: avoid crash on large invalid fp valueTodd Poynor2012-10-191-1/+1
| | | | | | | | | | | | | | | | | | Wraparound on invalid frame pointer (signed) -4 <= fp <= -1 defeats check for too high. Change-Id: Iaccb5d380e989660c06c0379a5e4ee31d9f84966 Signed-off-by: Todd Poynor <toddpoynor@google.com> Signed-off-by: Aleksandar Momiroski <alex.momir@ti.com>
* | OMAP: McBSP: Fix rx_irq handling in omap_mcbsp_request.John Grossman2012-10-181-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix a logic error in omap_mcbsp_request in the TI McBSP libraries. Looks like this lib is trying to support a unit which has been around since OMAP1, but which has been evolving. In particular, the libraries are expecting there to be two different IRQs going into the GIC. One for TX and another for RX. This may have been true on older OMAPs, but on OMAP4, the TX and RX halves of each McBSP share a single IRQ routed to the GIC. The hwmod file for OMAP44xx attempts to signal this to the library by passing 0 for the RX IRQ. Someone has made some attempt in the lib to embrace the fact that there may only be one interrupt line by checking the rx_irq parameter and only attempting to request the IRQ if rx_irq >= 0. There is a problems with this. The hwmod file is passing 0 as the IRQ number. 0 is a legal IRQ number on OMAP 4; GIC IRQ IDs range from 0 to 127. The library code only registers for an rx_irq if one is passed to it by the hwmod definition, but it makes no attempt to embrace the fact that there is a shared IRQ line, not that there is a TX interrupt but no RX interrupt. As such, the IRQ handlers are split, and each assumes that if an interrupt fired, that it either signals a error, or if there is no error, then the TX (or RX) buffer must need service. IOW - the interrupt handlers are not fully decoding their IRQ status registers. To be correct, on systems with a shared IRQ, the handlers would both need to get called (right now, the RX handler is not called), and each handler would need to fully decoder their status, and not assume that because there was no (TX|RX) error, that the (TX|RX) buffers need service. This change fixes the initial issue by checking to see if the IRQ passed from hwmod is > 0 instead of >= 0. While 0 is a legal value for a system IRQ, it is not a legal value for any McBSP IRQ (and almost certainly never will be). I am not doing anything to fix the RX IRQ handler right now, mostly because I don't have a platform to test any changes on. It might be good to bring this to TI's attention, hopefully they can fix their shared IRQ issues themselves. Change-Id: I2f30a036595898f296f642df9a93a77caeec76a5 Signed-off-by: John Grossman <johngro@google.com> Signed-off-by: Ruslan Bilovol <ruslan.bilovol@ti.com>
* | MMC: Make sure PBIAS config matches VMMC supply.John Grossman2012-10-181-3/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | Depending on the system, VMMC may end up being 3 or 1.8v. It is important that the PBIAS cell be configured to match the supply. Fortunately, the PBIAS cell contains a handy detector which can determine what the supply is set to after PWRDNZ has been released. Use this detector to make sure that the cell is properly configured and does not damage itself. Change-Id: Id59ab8e4042efe0778a80f1476bcf8aa746e6cd6 Signed-off-by: John Grossman <johngro@google.com> Signed-off-by: Ruslan Bilovol <ruslan.bilovol@ti.com>
* | OMAP: mcbsp: Fix error checks of rx_irq.Mike J. Chen2012-10-181-2/+2
| | | | | | | | | | | | | | | | | | | | rx_irq is intialized via a call to platform_get_irq_byname(), which can return a negative error value. Also, zero is a valid irq. Fix checks that assumed non-zero values were the only valid rx_irq values. Change-Id: I6be171eefa5923021e4adccf71f21baad3383554 Signed-off-by: Mike J. Chen <mjchen@google.com> Signed-off-by: Ruslan Bilovol <ruslan.bilovol@ti.com>
* | ARM: OMAP: USB: Fix compiler warningsMike J. Chen2012-10-122-42/+4
| | | | | | | | | | | | Change-Id: I871e4429da55cfc79a6e1b01ffc1029032c14ef9 Signed-off-by: Mike J. Chen <mjchen@google.com> Signed-off-by: Ruslan Bilovol <ruslan.bilovol@ti.com>
* | OMAP: DMA: Set thread reservation for high-priority channelsMisael Lopez Cruz2012-10-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | Reserve one thread for write and one for read for high-priority channels. This configuration helps latency critical synchronized transfers: memory-peripheral and/or peripheral-memory. Change-Id: Ib8ecf32db126937820b1da04b183568c44143d64 Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com> Signed-off-by: John Grossman <johngro@google.com> Signed-off-by: Ruslan Bilovol <ruslan.bilovol@ti.com>
* | ARM: omap2: fiq_debugger: ifdef local_timer_irqs in dump_irqs()Scott Anderson2012-10-121-9/+10
| | | | | | | | | | | | | | | | | | | | | | The local_timer_irqs field is surrounded by #ifdef CONFIG_LOCAL_TIMERS in the irq_cpustat_t structure. Do the same for its usage in dump_irqs() so fiq_debugger can compile on non-SMP systems. Change-Id: Ie212d39b8c705f6815e00d86569bdb92b0c1e4c1 Signed-off-by: Scott Anderson <saa@google.com> Signed-off-by: Ruslan Bilovol <ruslan.bilovol@ti.com>
* | ARM: omap2: Fix compile error on pm34xx.cScott Anderson2012-10-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Recently, a call to omap_pm_apply_min_bus_tput was added to pm34xx.c. This caused the following compile error: arch/arm/mach-omap2/pm34xx.c: In function 'omap3_pm_init': arch/arm/mach-omap2/pm34xx.c:926: error: implicit declaration of function 'omap_pm_apply_min_bus_tput' Adding an include of plat/omap-pm.h fixes this. Change-Id: Ia12054a1fb32ef007ab2470f42e19e190c726ee0 Signed-off-by: Scott Anderson <saa@google.com> Signed-off-by: Ruslan Bilovol <ruslan.bilovol@ti.com>
* | Fix mach-omap2/omap-iommu.c to prevent NULL pointer deref and fix a warning.Scott Anderson2012-10-121-3/+2
| | | | | | | | | | Change-Id: Iee7790cd529d8823b8c0606a3e4e614e94df0a77 Signed-off-by: Ruslan Bilovol <ruslan.bilovol@ti.com>
* | Enable the ARM security extension when compiling some filesJason Simmons2012-10-121-1/+2
| | | | | | | | | | | | Change-Id: I5704b5b0edc55b66d4917352198d921f246ad404 Signed-off-by: Jason Simmons <jsimmons@google.com> Signed-off-by: Ruslan Bilovol <ruslan.bilovol@ti.com>
* | board: tablet: usb: coexisting both HSIC and PHY in single kernel binaryRuslan Bilovol2012-10-054-5/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | Added kernel command line parameter 'omap4_tablet_uses_hsic' that allows to have both HSIC and PHY in single kernel binary for Tablet2, this allows to enable HSIC changing only kernel command line Usage: pass 'omap4_tablet_uses_hsic' to kernel through command line in case of HSIC modifications on Tablet2. Do naot apss it in case of traditional PHY usage. Change-Id: I0c50a1af18a26b06ca3957b21c7fa707d870428b Signed-off-by: Ruslan Bilovol <ruslan.bilovol@ti.com>
* | board: tablet: usb: remove HSIC reset pinRuslan Bilovol2012-10-051-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now when issues with cold start of USB is fixed, we can safely remove resetting of HSIC device Next HW changes are NOT NEEDED now: 3) modification for reset ability: - DNI R322 - solder a wire from U65.5 to U72.2 4) S1 switches: 7 - OFF, 8 - ON Change-Id: I4ef7af75441ecde089e40888784198e75a346275 Signed-off-by: Ruslan Bilovol <ruslan.bilovol@ti.com>
* | Revert "OMAP4: early mux initialization for EHCI"Ruslan Bilovol2012-10-051-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 5a2e0ba0863d099bbb454a303e8927b54d4f22bf. Reverted commit does USB Host muxes initialization too early. In case of HSIC connection, this generates IDLE state on the line before USB Host initialization. But HSIC Device generates CONNECT on the bus as soon as detects IDLE. However, since USB Host is initialized later, it misses this event. Change-Id: I90219bce6d55bc828ea5b76f6cf9efa272f28e0b Signed-off-by: Ruslan Bilovol <ruslan.bilovol@ti.com>
* | board: tablet: usb: enable HSIC disconnect-reconnectRuslan Bilovol2012-10-051-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | Next HW changes needed on Tablet2 before applying this patch: - DNI C230 Switch S5 may be used for emulating HSIC disconnect-reconnect, or be in the 'OFF' state if connected to Device's AUX. Change-Id: I8084d929b8f05c541af1caf12b1bc3ef007035d9 Signed-off-by: Ruslan Bilovol <ruslan.bilovol@ti.com>
* | ehci: omap: add HSIC disconnect-reconnect functionalityRuslan Bilovol2012-10-052-0/+8
| | | | | | | | | | | | | | | | | | | | | | Added HSIC disconnect-reconnect functionality using AUX pin. Disconnect or reconnect may be initiated by Device (using AUX pin) as well as by Host (through sysfs entries). Reimplemented .hub_status_data and .hub_control functions, implemented .disconnect and .reconnect ones. Change-Id: If697c06a4ef39ccaabb7c96dbcc0c597e7780515 Signed-off-by: Ruslan Bilovol <ruslan.bilovol@ti.com>
* | board: tablet: usb: enable HSICRuslan Bilovol2012-10-052-28/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is needed together with next Tablet2 HW modification 1) replace USB2640 by USB4640 2) change resistor strapping as follow: - Install R227, R228, R247, R248, R271, R276, R323, and L22 - DNI: R213, R214, R237, R238, R255, R256, R319 and L21 3) modification for reset ability: - DNI R322 - solder a wire from U65.5 to U72.2 4) S1 switches: 7 - OFF, 8 - ON Change-Id: I8937c65d22026bc4d4365b0070e25bcb33bc3a89 Signed-off-by: Ruslan Bilovol <ruslan.bilovol@ti.com>
* | usb: omap4: add HSIC supportRuslan Bilovol2012-10-051-0/+64
| | | | | | | | | | | | | | | | | | The OMAP4 HS USB host subsystem supports the configurations with two HSIC interfaces. This patch adds the ability to use both of them Change-Id: I95478563e07bba6811fed56abe442e640ccd71e4 Signed-off-by: Ruslan Bilovol <ruslan.bilovol@ti.com>
* | blaze_defconfig: build Bluetooth as modulesPavan Savoy2012-10-011-7/+17
| | | | | | | | | | | | | | | | | | Build the Bluetooth sub-system and the drivers as modules. This is to enable building the Bluetooth sub-system and drivers via the compat-wireless approach for enabling BlueTI. Change-Id: I9465b5fc8ff651c167e48920726592a5080926e6 Signed-off-by: Pavan Savoy <pavan_savoy@ti.com>
* | twl6030 battery: pass nominal capacity from board fileAnand Gadiyar2012-09-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Pass the nominal battery capacity from the board file instead of hardcoding it in the driver. TODO: This needs to be done for the blaze as well, although it's rarely run off the battery Change-Id: I15cba65f062c70f3b1e26f3c03db59e3af0d6ea9 Signed-off-by: Sivakumar Pothireddy <sivakumar.pothireddy@ti.com> Signed-off-by: Anand Gadiyar <gadiyar@ti.com>
* | ARM: OMAP4: Tablet: Add new board revisionVolodymyr Riazantsev2012-09-214-2/+10
| | | | | | | | | | | | | | Adding new (2158-004) board revision for Tablet2. Change-Id: I9e3c914f8c79d8b29cd1ebb76509210ecccb33e2 Signed-off-by: Volodymyr Riazantsev <v.riazantsev@ti.com>
* | OMAP4: USB: remove unused function twl6030_set_phy_clkRuslan Bilovol2012-09-124-4/+1
| | | | | | | | | | | | | | | | This function is redundant and not used anywhere. Remove it and change associated code accordingly Change-Id: I06ba222429cfe89a401b426a211d1752e646450a Signed-off-by: Ruslan Bilovol <ruslan.bilovol@ti.com>
* | OMAP4: DPLL cascading: Added dummy symbols to support external modulesIvan Khoronzhuk2012-09-112-1/+24
| | | | | | | | | | | | | | | | | | The DPLL cascading is used in external modules, so if the DPLL cascading is disabled, the external modules couldn't be added by reason the lack of needed symbols. Change-Id: I5d5e54e04dddbb20e60d2115c81f2c4362eccc5b Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* | OMAP4470: OPP: Change IVA OPP100 to CORE OPP dependencyOleksandr_Tyshchenko2012-09-071-1/+1
| | | | | | | | | | | | | | | | | | | | From timing closure point only VDD_CORE should be scaled to OPP100 level for IVA to be able to work at OPP100. L3 frequency can stay at 116MHz. So CORE OPP100H can be used as dependent OPP for IVA OPP100. Change-Id: I2493a4c45d81ebfbfd24600a90bd4ea2d3782c24 Signed-off-by: Oleksandr_Tyshchenko <oleksandr.tyshchenko@ti.com>
* | ARM: OMAP: HS USB Host: fix unbalanced pm callsRuslan Bilovol2012-09-051-22/+13
| | | | | | | | | | | | | | | | | | | | | | There is an issue with unbalanced pm calls. Only EHCI or only OHCI works good but not together. Issue appears when OHCI suspends whereas EHCI is active or vice versa - anyway all HSUSBHOST goes to suspend. This patch fixes this issue. Change-Id: Ie4c4e4d4ff210c8ceeec4415569660f8646e8ed5 Signed-off-by: Ruslan Bilovol <ruslan.bilovol@ti.com>
generated by cgit v1.1 at 2025-08-21 21:44:07 +0000