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* espresso defconfig: enable ath9k, do some hardening and disable TEE-related ↵HEADreplicant-6.0Wolfgang Wiedmeyer2017-06-121-1/+9
| | | | | | | | | driver code Ensure that heap randomization is enabled all the time. Enable stack-protector mode and seccomp. Signed-off-by: Wolfgang Wiedmeyer <wolfgit@wiedmeyer.de>
* espresso: resolve 3.0/3.4 kernel madness about board properties sysfsAndreas Blaesius2017-03-271-0/+24
| | | | | | Also add /sys/board/type which is a duplicate of /sys/board_properties/type Change-Id: Ia67318ea4fa7fc8c48b670953cc40b7ab35dd18b
* arm: fix handling of F_OFD_... in oabi_fcntl64()Al Viro2017-03-171-35/+36
| | | | | | | Change-Id: I75054f88e8c2c10a61b100a20b00bfbf09ff7c4d Cc: stable@vger.kernel.org # 3.15+ Reviewed-by: Jeff Layton <jeff.layton@primarydata.com> Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
* Update espresso10 touch firmwareAndreas Blaesius2016-09-231-1/+1
| | | | | | | (from GT-P5100_JB_Opensource_Update3 & GT-P5100_JB_Opensource kernel source) Change-Id: I5060d2486fd3a301820bc9e15f53029f65766c46
* espresso: sensor: remove system_rev check on gp2a_light_adc_valueAndreas Blaesius2016-09-181-4/+1
| | | | | | - fixes adaptive brightness on p3100 Change-Id: I4d44d1a2cc2e14dc4fc3a9d078f957aff265c41a
* OMAP4: espresso: adapt to dynamic secure_input heap allocationZiyan2016-09-152-1/+7
| | | | Change-Id: I574027d05632c363be830dfd5e618f55bbd33fff
* OMAP4: ion: dynamically allocate secure_input heap when dynamic tiler ↵Ziyan2016-09-151-1/+2
| | | | | | allocations are enabled Change-Id: Id7d88698b27add11170405387e90e7338a03cbab
* espresso: sensors: add missing gp2a_power functionZiyan2016-09-151-0/+6
| | | | | | | fixes: [ 0.963623] gp2a_i2c_probe: incomplete pdata! Change-Id: Ic1b7ecb35ec17c98da33fcadc63c30881fc875e0
* espresso: pmic: fix typoZiyan2016-07-051-1/+1
| | | | Change-Id: I88f02f175ca419cac6350bea5bfecacddf6260bf
* espresso: remove incomplete support for FB_OMAP_BOOTLOADER_INITZiyan2016-07-033-60/+0
| | | | | | Unfortunately, fixing this is hopeless with our old, proprietary Samsung bootloader. Change-Id: Iea4449e6f7060a4b497fc32e0f3cfc424dcc92de
* Partially revert "espresso: pmic: update configuration"Andreas Blaesius2016-06-181-11/+17
| | | | | | | | | | Add back espresso/espresso10 distinction to fix battery drain - don't revert the remove of unused bestbuy variant specific changes - don't revert the remove of unused REGULATOR_SUPPLY definitions - don't revert espresso10 specific .num_consumer_supplies Change-Id: I1ba0b2d0bcdfae66dc58eb1146f77db8bbbe7892
* espresso: add defconfig for KitKatAndreas Blaesius2016-06-061-0/+464
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* espresso: connector: rename dock audio switchZiyan2016-06-061-1/+1
| | | | Change-Id: If86f513d69d7d1f948a1778cc7956df4189aaf1a
* espresso: wifi: calculate MAC address based on the die IDZiyan2016-06-061-8/+6
| | | | | | | | | | | The Samsung BCMDHD used to read the factory MAC address from /efs. Accessing the filesystem in-kernel is a very bad practice, but what can we expect from Samsung? This commit calculates the MAC address based on the SoC Die ID: this is unique for all devices, and ensures that the same device will always have the same MAC address, not a randomly generated one. Change-Id: Ie62935f79149e82c62462828880de2610b93ee5f
* espresso: wifi: remove old CONFIG_DHD_USE_STATIC_BUF supportZiyan2016-06-061-73/+0
| | | | | | This is probably broken, and it's very unlikely that we'll ever need it. Change-Id: I93f46a8d1bbd5d6ac5f16a93daff6e7f8add10fb
* espresso: enable LZ4-backed zRAMZiyan2016-06-051-1/+7
| | | | Change-Id: I5cfad3130eaa944b1b2ece7561034502919cfcb7
* espresso_defconfig: enable F2FSAndreas Blaesius2016-06-051-0/+4
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* espresso: serial: fix i2c6 GPIO on bby variantsZiyan2016-05-171-1/+1
| | | | | | Fixes a bug which was introduced in commit f2eed54 Change-Id: I914566486155ee8f94beba6b9d9dbd5d0cec8af9
* espresso: power: fix i2c5 GPIOs on bby variantsZiyan2016-05-171-0/+6
| | | | | | Fixes a bug in gpio_i2c5 device register which was introduced in commit e1b8004 Change-Id: I9f2b007cc4293fba2d0c8ac6778eaa1e968c078d
* espresso: fix connector if CONFIG_BATTERY_MANAGER is not setZiyan2016-05-133-3/+38
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* configs: add espresso defconfigZiyan2016-05-051-0/+455
| | | | Based on the Android recommended config.
* espresso: pmic: fix suspend regressionZiyan2016-05-051-1/+1
| | | | | Commit f241f28 introduced a suspend regression: it seems like disabling vaux2 immediately wakes up the device, hence it can't stay in suspend.
* ARM: add Espresso muxtblAndreas Blaesius2016-05-0519-1/+3161
| | | | Based on the sources from GT-P3110_JB_Opensource.
* ARM: OMAP4: add Espresso supportAndreas Blaesius2016-05-0519-0/+5660
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on the sources from GT-P3110_JB_Opensource, plus a lot of cleanups and commonisation: * 7376125 sec: remove sec_debug * 5bbd0ed espresso10: remove support for chinese espresso variants * 2268c59 [WIP] Unify espresso/espresso10 * f4fc754 Unify espresso/espresso10: connector * e5b79a5 Unify espresso/espresso10: main board file, board detection functions * 33ebb62 espresso: bluetooth: cleanup * e9d2f3d board-espresso-connector.c: add missing espresso10 check * 294e783 espresso: rename espresso_is_espresso10 to board_is_espresso10 * c10890e board-espresso-connector.c: remove broken mhl gpios part * 696751c Remove unnecessary CONFIG_USB_HOST_NOTIFY * 3531c0b espresso: fix sec_muxtbl_init for p5113 variants * 085506f espresso: connector: remove usage of omap_muxtbl * 1bbf98c Remove SII9234 support * ab7e412 Rename SND_OMAP_SOC_WM8994 to SND_OMAP_SOC_ESPRESSO * c839206 espresso: round to closest valid pixel clocks * a8145af panel-ltn: commonize ltn070nl01 and ltn101al03 * 10b9598 espresso: display: update clock settings on init * acceb03 espresso: display: cleanup * d4baea7 espresso: emif: don't duplicate jedec timings * dcb93bd Unify espresso/espresso10: input * 5d5b22d espresso: input: get rid of omap_muxtbl, minor cleanups * b9b6413 Input and sensors layouts for landscape screen orientation * 6d9d26b espresso: irled: remove usage of omap_muxtbl, minor cleanups * a719b1b sec_jack: remove factory test stuff * 3042e05 espresso: switch to twl6030 gpadc * ce44fbe espresso: jack: remove usage of omap_muxtbl * 1d546e4 drivers: modem_if_v2: cleanup * a741bd5 espresso: modem: get rid of omap_muxtbl * 30f92e1 espresso: clean up PMIC board files * 5e3bc1c Unify espresso/espresso10: pmic * 5d02a5e espresso: pmic: fix annoying warnings * f241f28 espresso: pmic: update configuration * fd09f20 ASoC: wm8994: move SND_USE_SUB_MIC compile-time define to pdata * fc5d5a3 espresso: register fixed voltage regulator for mmc1 * 03b338e espresso: pmic: remove omap_muxtbl, minor cleanups * 63594e6 ASoC: omap_wm8994: get rid of omap_muxtbl, not so minor cleanups * 2709b8d espresso: pmic: fix twl6030_power_init on espresso10 * e1a5679 power: max17042_battery: move current range and sdi compensation to pdata * 41cd8c1 espresso: move bootmode setup to board files * e1b8004 espresso: power: remove usage of omap_muxtbl, cleanup * 0672d8d espresso: sdio: cleanup * b34632e Unify espresso/espresso10: sensors * 43ff628 espresso: set sensor orientations via pdata * 754db03 espresso: Update sensor board * f25245b espresso: sensors: get rid of omap_muxtbl, minor cleanups * 3a4cda1 espresso: serial: don't try to register i2c.8 on non-bby variants * f2eed54 espresso: serial: get rid of omap_muxtbl, minor cleanups * 0878522 espresso: vibrator: get rid of omap_muxtbl * 1a28ee3 espresso: update wifi setup * 4456fba espresso: wifi: get rid of omap_muxtbl
* OMAP4: ion: define heap sizes via pdataZiyan2016-05-012-8/+10
| | | | | | Various devices use fine-tuned heap sizes in their Ducati, so let's define these heap sizes via pdata instead of putting in ifdefs for every supported device here.
* [espresso] ARM: add OMAP4_ESPRESSO mach typeZiyan2016-04-301-0/+1
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* [espresso] OMAP4: UART: add DEBUG_LL support for espressoZiyan2016-04-301-0/+3
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* [espresso] OMAP4: TWL: use TWL6032 SR registers on espressoZiyan2016-04-301-0/+10
| | | | | Espresso hardware has TWL6032 PMIC with OMAP4430, so update the register settings to reflect that.
* omap4: ion: add config option to force dynamic tiler allocationsLuden2016-04-302-0/+10
| | | | Change-Id: I35aa150bdeda21b063591cd18ef55f01a6171e8c
* OMAP4: SAR: fix build when CONFIG_MFD_OMAP_USB_HOST is not setZiyan2016-04-301-0/+2
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* ARM: 7206/1: Add generic ARM instruction set condition code checks.Leif Lindholm2016-04-303-1/+93
| | | | | | | | | | | | This patch breaks the ARM condition checking code out of nwfpe/fpopcode.{ch} into a standalone file for opcode operations. It also modifies the code somewhat for coding style adherence, and adds some temporary variables for increased readability. Change-Id: I9935fbdebff9ddd263007412edd6a2b3eb06ae69 Signed-off-by: Leif Lindholm <leif.lindholm@arm.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* arm/traps: get full DIV instruction in thumb modeMichael Gernoth2016-03-111-0/+13
| | | | Change-Id: Ie60d2124d7835e85f03008d3dfe259b70490b4f2
* arm: add SDIV/UDIV emulation for ARMv7 processorsVladimir Murzin2016-03-113-0/+222
| | | | | | | | | | | | | | | | | | | | The Virtualization Extensions introduce the requirement for an ARMv7-A implementation to include SDIV and UDIV. Any implementation of the Virtualization Extensions must include the SDIV and UDIV instructions in the Thumb and ARM instruction sets. In an ARMv7-A implementation that does not include the Virtualization Extensions, it is IMPLEMENTATION DEFINED whether: * SDIV and UDIV are not implemented * SDIV and UDIV are implemented only in the Thumb instruction set * SDIV and UDIV are implemented in the Thumb and ARM instruction sets. This patch adds a handler to trap and emulate unimplemented SDIV and UDIV instructions in ARM and Thumb modes. Also some basic statistic is exported via /proc/cpu/idiv_emulation Change-Id: I8e721ecac62a05fab42ed7db7951b4c837a59bc7 Signed-off-by: Vladimir Murzin <murzin.v@gmail.com>
* ARM: disable preemption in machine_shutdownMike J. Chen2016-03-111-0/+9
| | | | | | | | | | | | | | | | | Since the smp call to stop the other cpus are handled in those cpus in interrupt context, there's a potential for those smp handlers to interrupt threads holding spin locks (such as the one a mutex holds). This prevents those threads from ever releasing their spin lock, so if the cpu doing the shutdown is allowed to switch to another thread that tries to grab the same lock/mutex, we could get into a deadlock (the spin lock call is called with preemption disabled in the mutex lock code). To avoid that possibility, disable preemption before doing the smp_send_stop(). Change-Id: I7976c5382d7173fcb3cd14da8cc5083d442b2544 Signed-off-by: Mike J. Chen <mjchen@google.com>
* ARM: 8120/1: crypto: sha512: add ARM NEON implementationJussi Kivilinna2016-03-113-0/+762
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds ARM NEON assembly implementation of SHA-512 and SHA-384 algorithms. tcrypt benchmark results on Cortex-A8, sha512-generic vs sha512-neon-asm: block-size bytes/update old-vs-new 16 16 2.99x 64 16 2.67x 64 64 3.00x 256 16 2.64x 256 64 3.06x 256 256 3.33x 1024 16 2.53x 1024 256 3.39x 1024 1024 3.52x 2048 16 2.50x 2048 256 3.41x 2048 1024 3.54x 2048 2048 3.57x 4096 16 2.49x 4096 256 3.42x 4096 1024 3.56x 4096 4096 3.59x 8192 16 2.48x 8192 256 3.42x 8192 1024 3.56x 8192 4096 3.60x 8192 8192 3.60x Change-Id: Ibc318f8c9136507f57e2bb8d8f51b4714d8ed70b Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Jussi Kivilinna <jussi.kivilinna@iki.fi> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Iliyan Malchev <malchev@google.com>
* ARM: 8119/1: crypto: sha1: add ARM NEON implementationJussi Kivilinna2016-03-115-3/+848
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds ARM NEON assembly implementation of SHA-1 algorithm. tcrypt benchmark results on Cortex-A8, sha1-arm-asm vs sha1-neon-asm: block-size bytes/update old-vs-new 16 16 1.04x 64 16 1.02x 64 64 1.05x 256 16 1.03x 256 64 1.04x 256 256 1.30x 1024 16 1.03x 1024 256 1.36x 1024 1024 1.52x 2048 16 1.03x 2048 256 1.39x 2048 1024 1.55x 2048 2048 1.59x 4096 16 1.03x 4096 256 1.40x 4096 1024 1.57x 4096 4096 1.62x 8192 16 1.03x 8192 256 1.40x 8192 1024 1.58x 8192 4096 1.63x 8192 8192 1.63x Change-Id: I6df3c0a9ba8d450d034cf78785b6ce80a72bef4a Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Jussi Kivilinna <jussi.kivilinna@iki.fi> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Iliyan Malchev <malchev@google.com>
* ARM: 8118/1: crypto: sha1/make use of common SHA-1 structuresJussi Kivilinna2016-03-111-28/+22
| | | | | | | | | | | Common SHA-1 structures are defined in <crypto/sha.h> for code sharing. This patch changes SHA-1/ARM glue code to use these structures. Change-Id: I5b82530706fa7c6f5ec08926992b86d26fa1c24d Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Jussi Kivilinna <jussi.kivilinna@iki.fi> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* crypto: arm-aes - fix encryption of unaligned dataMikulas Patocka2016-03-111-5/+5
| | | | | | | | | | | Fix the same alignment bug as in arm64 - we need to pass residue unprocessed bytes as the last argument to blkcipher_walk_done. Change-Id: Ia4d3cacb006269aa5b9c0c542256eff5822e84ac Signed-off-by: Mikulas Patocka <mpatocka@redhat.com> Cc: stable@vger.kernel.org # 3.13+ Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* CRYPTO: Fix more AES build errorsRussell King2016-03-112-2/+2
| | | | | | | | | | | | | | | | | | | | | Building a multi-arch kernel results in: arch/arm/crypto/built-in.o: In function `aesbs_xts_decrypt': sha1_glue.c:(.text+0x15c8): undefined reference to `bsaes_xts_decrypt' arch/arm/crypto/built-in.o: In function `aesbs_xts_encrypt': sha1_glue.c:(.text+0x1664): undefined reference to `bsaes_xts_encrypt' arch/arm/crypto/built-in.o: In function `aesbs_ctr_encrypt': sha1_glue.c:(.text+0x184c): undefined reference to `bsaes_ctr32_encrypt_blocks' arch/arm/crypto/built-in.o: In function `aesbs_cbc_decrypt': sha1_glue.c:(.text+0x19b4): undefined reference to `bsaes_cbc_encrypt' This code is already runtime-conditional on NEON being supported, so there's no point compiling it out depending on the minimum build architecture. Change-Id: Iff65acec7d30c508bf72132acad67332ea56bd3b Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: add .gitignore entry for aesbs-core.SRussell King2016-03-111-0/+1
| | | | | | | This avoids this file being incorrectly added to git. Change-Id: If8d1d669d8565b1f1cf3751b202bae052d26b53b Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: add support for bit sliced AES using NEON instructionsArd Biesheuvel2016-03-114-2/+5457
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bit sliced AES gives around 45% speedup on Cortex-A15 for encryption and around 25% for decryption. This implementation of the AES algorithm does not rely on any lookup tables so it is believed to be invulnerable to cache timing attacks. This algorithm processes up to 8 blocks in parallel in constant time. This means that it is not usable by chaining modes that are strictly sequential in nature, such as CBC encryption. CBC decryption, however, can benefit from this implementation and runs about 25% faster. The other chaining modes implemented in this module, XTS and CTR, can execute fully in parallel in both directions. The core code has been adopted from the OpenSSL project (in collaboration with the original author, on cc). For ease of maintenance, this version is identical to the upstream OpenSSL code, i.e., all modifications that were required to make it suitable for inclusion into the kernel have been made upstream. The original can be found here: http://git.openssl.org/gitweb/?p=openssl.git;a=commit;h=6f6a6130 Note to integrators: While this implementation is significantly faster than the existing table based ones (generic or ARM asm), especially in CTR mode, the effects on power efficiency are unclear as of yet. This code does fundamentally more work, by calculating values that the table based code obtains by a simple lookup; only by doing all of that work in a SIMD fashion, it manages to perform better. Change-Id: Ife4f79ce9e8994e248d6fc01fcb23b0534265418 Cc: Andy Polyakov <appro@openssl.org> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ARM: move AES typedefs and function prototypes to separate headerArd Biesheuvel2016-03-112-16/+25
| | | | | | | | | Put the struct definitions for AES keys and the asm function prototypes in a separate header and export the asm functions from the module. This allows other drivers to use them directly. Change-Id: Ic79a7da83232d4e3658f3fc64de4761c88ae73f3 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ARM: 7837/3: fix Thumb-2 bug in AES assembler codeArd Biesheuvel2016-03-111-3/+3
| | | | | | | | | | | | | | | | commit 40190c85f427dcfdbab5dbef4ffd2510d649da1f upstream. Patch 638591c enabled building the AES assembler code in Thumb2 mode. However, this code used arithmetic involving PC rather than adr{l} instructions to generate PC-relative references to the lookup tables, and this needs to take into account the different PC offset when running in Thumb mode. Change-Id: I7358a145be3f37420c8ce5b8fc83a761b0d863ac Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* ARM: 7723/1: crypto: sha1-armv4-large.S: fix SP handlingArd Biesheuvel2016-03-111-1/+1
| | | | | | | | | | | | | | Make the SHA1 asm code ABI conformant by making sure all stack accesses occur above the stack pointer. Origin: http://git.openssl.org/gitweb/?p=openssl.git;a=commit;h=1a9d60d2 Change-Id: I89fe44b5021ee3d37ac924f04a82e9631e31843e Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Nicolas Pitre <nico@linaro.org> Cc: stable@vger.kernel.org Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7626/1: arm/crypto: Make asm SHA-1 and AES code Thumb-2 compatibleDave Martin2016-03-112-59/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes aes-armv4.S and sha1-armv4-large.S to work natively in Thumb. This allows ARM/Thumb interworking workarounds to be removed. I also take the opportunity to convert some explicit assembler directives for exported functions to the standard ENTRY()/ENDPROC(). For the code itself: * In sha1_block_data_order, use of TEQ with sp is deprecated in ARMv7 and not supported in Thumb. For the branches back to .L_00_15 and .L_40_59, the TEQ is converted to a CMP, under the assumption that clobbering the C flag here will not cause incorrect behaviour. For the first branch back to .L_20_39_or_60_79 the C flag is important, so sp is moved temporarily into another register so that TEQ can be used for the comparison. * In the AES code, most forms of register-indexed addressing with shifts and rotates are not permitted for loads and stores in Thumb, so the address calculation is done using a separate instruction for the Thumb case. The resulting code is unlikely to be optimally scheduled, but it should not have a large impact given the overall size of the code. I haven't run any benchmarks. Change-Id: Ic80ff883d90ee1f83b775e0bb447672d81dff54b Signed-off-by: Dave Martin <dave.martin@linaro.org> Tested-by: David McCullough <ucdevel@gmail.com> (ARM only) Acked-by: David McCullough <ucdevel@gmail.com> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* arm/crypto: Add optimized AES and SHA1 routinesDavid McCullough2016-03-116-0/+1912
| | | | | | | | | | | | | | Add assembler versions of AES and SHA1 for ARM platforms. This has provided up to a 50% improvement in IPsec/TCP throughout for tunnels using AES128/SHA1. Platform CPU SPeed Endian Before (bps) After (bps) Improvement IXP425 533 MHz big 11217042 15566294 ~38% KS8695 166 MHz little 3828549 5795373 ~51% Change-Id: I5b77e7aa89c8b1d54aef75065827325e90305638 Signed-off-by: David McCullough <ucdevel@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* Merge remote-tracking branch 'linux-stable/linux-3.0.y' into ↵Ziyan2015-10-2542-235/+234
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | p-android-omap-3.0-dev-espresso Conflicts: Makefile arch/arm/include/asm/hardware/cache-l2x0.h arch/arm/kernel/smp.c arch/arm/mach-omap2/board-4430sdp.c arch/arm/mach-omap2/board-omap4panda.c arch/arm/mach-omap2/opp.c arch/ia64/include/asm/futex.h drivers/bluetooth/ath3k.c drivers/bluetooth/btusb.c drivers/firmware/efivars.c drivers/gpu/drm/i915/intel_lvds.c drivers/gpu/drm/radeon/radeon_atombios.c drivers/gpu/drm/radeon/radeon_irq_kms.c drivers/hwmon/fam15h_power.c drivers/mfd/twl6030-irq.c drivers/mmc/core/sdio.c drivers/net/tun.c drivers/net/usb/ipheth.c drivers/net/usb/usbnet.c drivers/usb/core/hub.c drivers/usb/host/xhci-mem.c drivers/usb/host/xhci.h drivers/usb/musb/omap2430.c drivers/usb/serial/ftdi_sio.c drivers/usb/serial/ftdi_sio_ids.h drivers/usb/serial/option.c drivers/usb/serial/qcserial.c drivers/usb/serial/ti_usb_3410_5052.c drivers/usb/serial/ti_usb_3410_5052.h drivers/video/omap2/dss/hdmi.c fs/splice.c include/asm-generic/pgtable.h include/net/sch_generic.h kernel/cgroup.c kernel/futex.c kernel/time/timekeeping.c net/ipv4/route.c net/ipv4/syncookies.c net/ipv4/tcp_ipv4.c net/wireless/util.c security/commoncap.c sound/soc/soc-dapm.c
| * ARM: PCI: versatile: Fix SMAP register offsetsPeter Maydell2013-09-261-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 99f2b130370b904ca5300079243fdbcafa2c708b upstream. The SMAP register offsets in the versatile PCI controller code were all off by four. (This didn't have any observable bad effects because on this board PHYS_OFFSET is zero, and (a) writing zero to the flags register at offset 0x10 has no effect and (b) the reset value of the SMAP register is zero anyway, so failing to write SMAP2 didn't matter.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * ARM: 7080/1: l2x0: make sure I&D are not locked down on initLinus Walleij2013-08-202-2/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit bac7e6ecf60933b68af910eb4c83a775a8b20b19 upstream. Fighting unfixed U-Boots and other beasts that may the cache in a locked-down state when starting the kernel, we make sure to disable all cache lock-down when initializing the l2x0 so we are in a known state. Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reported-by: Jan Rinze <janrinze@gmail.com> Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Cc: Rabin Vincent <rabin.vincent@stericsson.com> Cc: Adrian Bunk <adrian.bunk@movial.com> Cc: Rob Herring <robherring2@gmail.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Tested-by: Robert Marklund <robert.marklund@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * ARM: 7765/1: perf: Record the user-mode PC in the call chain.Jed Davis2013-07-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit c5f927a6f62196226915f12194c9d0df4e2210d7 upstream. With this change, we no longer lose the innermost entry in the user-mode part of the call chain. See also the x86 port, which includes the ip. It's possible to partially work around this problem by post-processing the data to use the PERF_SAMPLE_IP value, but this works only if the CPU wasn't in the kernel when the sample was taken. Signed-off-by: Jed Davis <jld@mozilla.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
generated by cgit v1.1 at 2025-06-18 00:13:06 +0000