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* Merge remote-tracking branch 'linux-stable/linux-3.0.y' into ↵Ziyan2015-10-252-5/+3
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | p-android-omap-3.0-dev-espresso Conflicts: Makefile arch/arm/include/asm/hardware/cache-l2x0.h arch/arm/kernel/smp.c arch/arm/mach-omap2/board-4430sdp.c arch/arm/mach-omap2/board-omap4panda.c arch/arm/mach-omap2/opp.c arch/ia64/include/asm/futex.h drivers/bluetooth/ath3k.c drivers/bluetooth/btusb.c drivers/firmware/efivars.c drivers/gpu/drm/i915/intel_lvds.c drivers/gpu/drm/radeon/radeon_atombios.c drivers/gpu/drm/radeon/radeon_irq_kms.c drivers/hwmon/fam15h_power.c drivers/mfd/twl6030-irq.c drivers/mmc/core/sdio.c drivers/net/tun.c drivers/net/usb/ipheth.c drivers/net/usb/usbnet.c drivers/usb/core/hub.c drivers/usb/host/xhci-mem.c drivers/usb/host/xhci.h drivers/usb/musb/omap2430.c drivers/usb/serial/ftdi_sio.c drivers/usb/serial/ftdi_sio_ids.h drivers/usb/serial/option.c drivers/usb/serial/qcserial.c drivers/usb/serial/ti_usb_3410_5052.c drivers/usb/serial/ti_usb_3410_5052.h drivers/video/omap2/dss/hdmi.c fs/splice.c include/asm-generic/pgtable.h include/net/sch_generic.h kernel/cgroup.c kernel/futex.c kernel/time/timekeeping.c net/ipv4/route.c net/ipv4/syncookies.c net/ipv4/tcp_ipv4.c net/wireless/util.c security/commoncap.c sound/soc/soc-dapm.c
| * i2c: xiic: must always write 16-bit words to TX_FIFOSteven A. Falco2013-05-071-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit c39e8e4354ce4daf23336de5daa28a3b01f00aa6 upstream. The TX_FIFO register is 10 bits wide. The lower 8 bits are the data to be written, while the upper two bits are flags to indicate stop/start. The driver apparently attempted to optimize write access, by only writing a byte in those cases where the stop/start bits are zero. However, we have seen cases where the lower byte is duplicated onto the upper byte by the hardware, which causes inadvertent stop/starts. This patch changes the write access to the transmit FIFO to always be 16 bits wide. Signed off by: Steven A. Falco <sfalco@harris.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * i2c: davinci: Free requested IRQ in removeMarcus Folkesson2012-06-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | commit 9868a060ccf769c08ec378a9829137e272e9a92c upstream. The freed IRQ is not necessary the one requested in probe. Even if it was, with two or more i2c-controllers it will fails anyway. Signed-off-by: Marcus Folkesson <marcus.folkesson@gmail.com> Signed-off-by: Wolfram Sang <w.sang@pengutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * i2c: pnx: Disable clk in suspendRoland Stigge2012-05-071-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 6c557cfee08751d22aed34840f389b846f0f4508 upstream. In the driver's suspend function, clk_enable() was used instead of clk_disable(). This is corrected with this patch. Signed-off-by: Roland Stigge <stigge@antcom.de> Reviewed-by: Arnd Bergmann <arnd@arndb.de> [wsa: reworded commit header slightly] Signed-off-by: Wolfram Sang <w.sang@pengutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * i2c-algo-bit: Fix spurious SCL timeouts under heavy loadVille Syrjala2012-03-191-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 8ee161ce5e0cfc689eb677f227a6248191165fac upstream. When the system is under heavy load, there can be a significant delay between the getscl() and time_after() calls inside sclhi(). That delay may cause the time_after() check to trigger after SCL has gone high, causing sclhi() to return -ETIMEDOUT. To fix the problem, double check that SCL is still low after the timeout has been reached, before deciding to return -ETIMEDOUT. Signed-off-by: Ville Syrjala <syrjala@sci.fi> Signed-off-by: Jean Delvare <khali@linux-fr.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * i2c: mxs: only flag completion when queue is completely doneWolfram Sang2012-03-121-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 844990daa2e69a4258049ba9c2bae1180657dac3 upstream. The hardware generates an interrupt for every completed command in the queue while the code assumed that it will only generate one interrupt when the queue is empty. So, explicitly check if the queue is really empty. This patch fixed problems which occurred due to high traffic on the bus. While we are here, move the completion-initialization after the parameter error checking. Signed-off-by: Wolfram Sang <w.sang@pengutronix.de> Cc: Shawn Guo <shawn.guo@linaro.org> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Lothar Waßmann <LW@KARO-electronics.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | I2C: omap: Fix error condition when slave sends a NAKMike J. Chen2012-10-181-0/+1
| | | | | | | | | | | | | | | | | | | | Fix an issue in the omap i2c host controller driver where it was not properly clearing out an error condition in the unit after a NAK'ed transaction causing the subsequent transaction to time out. Change-Id: I5cdc8e740acdbc8116dca4d13f1a2cee37f75582 Signed-off-by: Mike J. Chen <mjchen@google.com> Signed-off-by: Ruslan Bilovol <ruslan.bilovol@ti.com>
* | i2c: omap: implement shutdown handlerVikram Pandita2012-08-031-1/+30
| | | | | | | | | | | | | | | | | | | | | | | | Once i2c driver shutdown has been called, ignore any more transfer requests. This patch adds the missing callback. Leave the PMIC i2c (i2c-1) alive, since power_off case needs it well after shutdown handlers have been called for power_off case. Change-Id: I4f4553327e5c024f78acb8501864dd9beb1883c3 Signed-off-by: Semen Protsenko <semen.protsenko@ti.com> Signed-off-by: Vikram Pandita <vikram.pandita@ti.com>
* | OMAP: I2C: Wait till functional part of the I2C controller completely ↵Kohtaro Hashimoto2012-07-231-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | becomes valid Bus busy status bit is not effective when functional part of the I2C controller is not valid, and bus busy detection in omap_i2c_wait_for_bb() will be skipped sometimes. So we should wait till functional part of the I2C controller completely becomes valid, after setting the I2Ci.I2C_CON[15] I2C_EN bit to 1. For doing that we have to wait till RDONE bit of SYSS register reach "1". For details see TRM, 23.1.4.3 HS I2C Software Reset. Change-Id: I989855d6cb2b1aa0098e11245dacb77583fe6647 Signed-off-by: Semen Protsenko <semen.protsenko@ti.com>
* | OMAP: I2C: Disable interrupts in omap_i2c_bus_clear()Kohtaro Hashimoto2012-07-111-0/+5
| | | | | | | | | | | | | | | | | | | | Interrupts that occur during omap_i2c_bus_clear() can cause to erroneous behaviour in interrupt handler, i.e. multiple printing of "RRDY IRQ while no data requested" message. So disable interrupts in omap_i2c_bus_clear() function since they can't be handled correctly. Change-Id: If4525c93284766d0a2705d7ca4d1f962e3cc4b15 Signed-off-by: Semen Protsenko <semen.protsenko@ti.com>
* | OMAP4: DPLL cascading: I2C psc reconfiguration to support DPLL cascadingMadhusudhan Chikkature2012-06-181-0/+155
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The I2C clocks change from 96MHz to 48MHz in dpll cascading mode.The I2C driver is registerd with DPLL cascading and the change in clocks is handled.The device speed of > 1Mbps is not supported in DPLL cascading mode. [Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>: Ported and adapted to p-android-omap-3.0] Change-Id: Ib37648012476a8246cc9e437f707b6e3969e13a3 Signed-off-by: Madhusudhan Chikkature <madhu.cr@ti.com> Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
* | Merge latest changes from google kernel/common.gitRoman Shaposhnikov2012-06-133-6/+18
| | | | | | | | | | | | | | Kernel version updated to 3.0.31 Change-Id: Ifbd7150801f3beeec9cbaa566f249d8019ef9348 Signed-off-by: Roman Shaposhnikov <x0166637@ti.com>
* | I2C: OMAP: NACK without STPJan Weitzel2012-04-041-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On OMAP4 OMAP_I2C_STAT_NACK is causing a timeout on the next access. The isr cleans all flags in OMAP_I2C_CON_REG by setting OMAP_I2C_CON_STP OMAP_I2C_CON_STP is also set in omap_i2c_xfer_msg on the last message. According to the TI TSR the sequence for OMAP_I2C_STAT_NACK and OMAP_I2C_STAT_AL are nearly the same. Removing the OMAP_I2C_CON_STP part in the isr fix the problem. Tested on OMAP4430 and OMAP3530 (here NACK was not a problem) Fixes also booting on 2430sdp. [Picked from http://patches.linaro.org/1899/] Change-Id: I9bdeba8853ced27659770ad9390bd1b4be573155 Signed-off-by: Jan Weitzel <j.weitzel@phytec.de> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Anand Gadiyar <gadiyar@ti.com>
* | Merge branch 'linux-3.0.18' into p-android-omap-3.0Dan Murphy2012-02-027-13/+23
|\ \ | |/ | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/mach-omap2/smartreflex.c drivers/i2c/busses/i2c-omap.c drivers/usb/host/ehci.h drivers/usb/musb/musb_core.c fs/proc/base.c Signed-off-by: Dan Murphy <dmurphy@ti.com>
| * i2c-eg20t: modified the setting of transfer rate.Toshiharu Okada2012-01-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | commit ff35e8b18984ad2a82cbd259fc07f0be4b34b1aa upstream. This patch modified the setting value of I2C Bus Transfer Rate Setting Counter regisrer. Signed-off-by: Toshiharu Okada <toshiharu-linux@dsn.okisemi.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * I2C: OMAP: correct SYSC register offset for OMAP4Alexander Aring2012-01-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | commit 2727b1753934e154931d6b3bdf20c9b2398457a2 upstream. Correct OMAP_I2C_SYSC_REG offset in omap4 register map. Offset 0x20 is reserved and OMAP_I2C_SYSC_REG has 0x10 as offset. Signed-off-by: Alexander Aring <a.aring@phytec.de> [khilman@ti.com: minor changelog edits] Signed-off-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * i2c: Fix error value returned by several bus driversJean Delvare2012-01-255-10/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | commit 7c1f59c9d5caf3a84f35549b5d58f3c055a68da5 upstream. When adding checks for ACPI resource conflicts to many bus drivers, not enough attention was paid to the error paths, and for several drivers this causes 0 to be returned on error in some cases. Fix this by properly returning a non-zero value on every error. Signed-off-by: Jean Delvare <khali@linux-fr.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * i2c-algo-bit: Generate correct i2c address sequence for 10-bit targetJeffrey (Sheng-Hui) Chu2011-12-091-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | commit cc6bcf7d2ec2234e7b41770185e4dc826390185e upstream. The wrong bits were put on the wire, fix that. This fixes kernel bug #42562. Signed-off-by: Sheng-Hui J. Chu <jeffchu@broadcom.com> Signed-off-by: Jean Delvare <khali@linux-fr.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* | I2C: enable IRQ only when bus is acquired.Huzefa N K2011-12-221-0/+7
| | | | | | | | | | | | | | Enable the interrupts only when I2C hw spinlock is acquired Change-Id: I610236a1c1150f5746546c7bd3a0fad6eff2e706 Signed-off-by: Huzefa Kankroliwala <huzefank@ti.com>
* | I2C: OMAP: Update recovery mechanism from Bus Busy conditionJon Hunter2011-12-151-14/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case a peripheral is driving SDA bus low (ie. a start condition), provide a constant clock output using the test mode of the OMAP I2C controller to try and clear the bus. Soft reset I2C controller after attempting the bus clear to ensure that controller is in a good state. Based upon Vikram Pandita's patch from TI Android 3.0 kernel and modified for mainline by Jon Hunter. A couple differences from the original patch ... 1. Add a new function for bus clear 2. Ensure that the CON.I2C_EN bit is set when using the SYSTEST feature to output a permanent clock. This bit needs to be set and tpyically it would be set by the unidle function but this is not the case for all OMAP generations. 3. Program the SYSTEST setting only the bits we care about. However, restore SYSTEST registers to there original state as some OMAP generations do not implement perform a soft-reset. 4. Clear the CON register after performing the bus clear, so when we call the init function the controller is disabled and the init function will re-enable later. Original patch can be found here: http://git.omapzoom.org/?p=kernel/omap.git;a=commit;h=a2ab04192ba25e60f95ba1ff3af5601a2d7b5bd1 Change-Id: I299357568aeafa4bff4caa5dedb294adbd80df36 Signed-off-by: Jon Hunter <jon-hunter@ti.com>
* | I2C: OMAP: Don't check if wait_for_completion_timeout() returns less than zeroJon Hunter2011-12-151-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | By definition, wait_for_completion_timeout() returns an unsigned value and therefore, it is not necessary to check if the return value is less than zero as this is not possible. Move the call to wait_for_completion_timeout() onto a single line as it is less than 80 characters. Change-Id: I906a112c1ef339aa0b7ad26896669fa413448fa8 Signed-off-by: Jon Hunter <jon-hunter@ti.com>
* | OMAP: I2C: Remove the SYSC register definitionShubhrajyoti D2011-12-151-5/+0
| | | | | | | | | | | | | | | | | | | | | | The SYSC register should not accessed in the driver removing the define from the driver. Also clean up the syscstate from the omap_i2c_dev struct. Change-Id: I95a7668de47a26523b51a9d13aea83b7aa7def03 Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com> Signed-off-by: Jon Hunter <jon-hunter@ti.com>
* | OMAP: I2C: Remove the reset in the init pathShubhrajyoti D2011-12-151-61/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - The reset in the driver at init is not needed anymore as the hwmod framework takes care of reseting it. - Reset is removed from omap_i2c_init, which was called not only during probe, but also after time out and error handling. device_reset were added in those places to effect the reset. - Earlier the hwmod SYSC settings were over-written in the driver. Removing the same and letting the hwmod take care of the settings. - Clean up the SYSS_RESETDONE_MASK macro as it is no longer needed. - Clean up the SYSCONFIG SYSC bit defination macros. - Fix the typos in wakeup. Change-Id: I8f4ccdf783de6fe3d883e4aa5290473ea0117945 Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com> Signed-off-by: Jon Hunter <jon-hunter@ti.com>
* | Merge branch 'android-omap-3.0' into p-android-omap-3.0Dan Murphy2011-11-091-2/+2
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * android-omap-3.0: (38 commits) OMAP:DSS:DSSCOMP: Avoid freeing a composition twice on set failure gpu: pvr: Update to DDK 1.8@550175 gpu: pvr: Update to DDK 1.8@334506 OMAP4: McASP: Move device creation to mach-omap2 omap: iovmm: move print to before free in sgtable_free OMAP4: temp_sensor: update throttling thresholds OMAP: clock: optimize dpll locking logic OMAP4: PM: Enable Auto VREF LPDDR I/O supply ion: fix build ASoC: omap-mcasp: Simplify device struct retrieval ASoC: omap-mcasp: Remove wrappers for start/stop ASoC: omap-mcasp: Remove redundant format check ASoC: omap-mcasp: Configure the channel status register ASoC: omap-mcasp: Relax allowed sample rates check usb: musb: omap2430: use proper signed variables net: wireless: bcm4329: Skip dhd_bus_stop() if bus is already down net: wireless: bcmdhd: Skip dhd_bus_stop() if bus is already down net: wireless: bcmdhd: Improve suspend/resume processing net: wireless: bcmdhd: Check if FW is Ok for internal FW call ion: export functions to enable usage by kernel modules ... Change-Id: I68419e93ae7b91ba33ddba06e853845caebb6905 Signed-off-by: Dan Murphy <dmurphy@ti.com>
| * | i2c: omap3: Fix accessing of invalid registersScott Anderson2011-11-031-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When cpu_is_omap44xx, dev->regs is set to point to omap4_reg_map[], which contains entries for OMAP_I2C_IRQENABLE_SET and OMAP_I2C_IRQENABLE_CLR. These entries are not present in the other reg_map. However, the code that uses these registers does not ensure that cpu_is_omap44xx before using them. This can cause register 0x00 (the revision register) to be accessed instead and the proper register to not be accessed. This problem was observed on the OMAP3630 and caused long hangs. The fix is to ensure that cpu_is_omap44xx before accessing the registers. Thanks to vikram pandita for pointing me in the right direction. Change-Id: Ic3accee9ce251724f13056bdb01f4db3308cd099 Signed-off-by: Scott Anderson <saa@google.com>
* | | OMAP4: Avoid clearing i2c2 irq on A9 when HWSPINLOCK is enabledChristina Warren2011-10-061-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is related to this commit: 7dd92cb9a8b9c6bb0f4b03afd26ea50ec90cfb73 On Blaze and Blaze Tablet, the i2c-2 bus is shared by A9 and Ducati. We want A9 to be able to access the i2c-2 bus when it needs it. This patch will prevent the i2c-2 irq from being cleared on A9 when Ducati requests the i2c-2 resource, since hwspinlock is being used to arbitrate the use of the i2c-2 bus. Change-Id: Iddb667f77e17d9799a9caa62d9f2a0a0043f1768 Signed-off-by: Christina Warren <cawarren@ti.com>
* | | Merge branch 'android-omap-3.0' into p-android-omap-3.0Dan Murphy2011-10-031-4/+13
|\ \ \ | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * android-omap-3.0: OMAP4: PM: remove suspend handler for SR Revert "OMAP3+: PM: SR: add suspend/resume handlers" OMAP4+: EMIF: make interrupts wakeup capable OMAP4460: PM: Allow SRAM LDO to attain retention during low power mode. OMAP4: PM: syscontrol: workaround LPDDR CK IO pull disable OMAP4: PM: syscontrol: Disable LPDDR VREF manual control i2c: omap: recover from Bus Busy condition OMAP: mcspi: Extend device config structure with swap_datalines param mtd: m25p80: add Winbond w25q80 chip support omap: rpmsg_resmgr: reserve i2c resources to a remoteproc i2c: omap: do not call i2c_detect_ext_master blindly during probe Change-Id: I3e9462cf99f893db77ed70636ee514e789ab2a7f Signed-off-by: Dan Murphy <dmurphy@ti.com>
| * | i2c: omap: recover from Bus Busy conditionVikram Pandita2011-09-291-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case a peripheral is holding the DATA bus low, provide a 400Khz constant clock output using the TEST register. Also soft reset the I2C controller so that there is no stale state left in the HW state machine. A WARN_ON() will be generated when a BB timeout happens. Change-Id: I23b824f6ae3435ea2e4abf0cbc047584b1e9b449 Signed-off-by: Vikram Pandita <vikram.pandita@ti.com>
| * | i2c: omap: do not call i2c_detect_ext_master blindly during probeIliyan Malchev2011-09-291-2/+0
| | | | | | | | | | | | | | | | | | | | | The decision to call i2c_detect_ext_master() must be made dynamically. This way we are locking out A9 I2C clients without any external requests. Signed-off-by: Iliyan Malchev <malchev@google.com>
* | | OMAP4: I2C: Add hwspinlock supportChristina Warren2011-09-281-0/+36
|/ / | | | | | | | | | | | | | | | | | | Adding support for hwspinlock in I2C driver in Blaze and Blaze_Tablet2. Also adding an api omap_i2c_get_hwspinlockid to be used by remote proc to populate the resource table. Change-Id: I5f554ead10806c90442359365dcb8ebff51bf2bf Signed-off-by: Christina Warren <cawarren@ti.com>
* | Revert "i2c: omap44xx: disable ARDY interrupt for each transfer"Simon Wilson2011-09-181-75/+6
| | | | | | | | | | | | Causes sensor and audio delays. This reverts commit f0526a82e8f65e8a9acdd6ad5eaea738b569a3a5.
* | i2c: omap: XUDF and ROVR is not fatalVikram Pandita2011-09-161-6/+3
| | | | | | | | | | | | | | | | | | Do not report XUDF or ROVR as an error to the driver making i2c transfer. Its an indication by OMAP hw that these conditions are hitting, but the real transfer should still go through Change-Id: Id721d0037a850d34e15dd070ec4e53dacc90a8c4 Signed-off-by: Vikram Pandita <vikram.pandita@ti.com>
* | i2c: omap44xx: disable ARDY interrupt for each transferVikram Pandita2011-09-161-6/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For indicating ready-for-next-transfer, there is ARDY interrupt. There is no need to have this interrupt enabled for indication of current transfer as complete. So resort to a combination of Interrupt and Polling mechanism. Interrupt mechanism for: RRDY/RDR and XRDY/XDR Polling mechanism for: ARDY Before a message is to be sent, check for ARDY status ready with a timeout protection. For one message the flow is: Fifo operation; one interrupt; Done Thus avoiding ARDY wait/interrupt altogether. For two/more message transfer the flow is: Fifo operation;one interrupt; wait_ardy(); fifo operation;Done Thus avoiding 2 ARDY interrupts, instead only one ardy wait Change-Id: Icf26731db373073bc300da2804979b5d509ac448 Signed-off-by: Vikram Pandita <vikram.pandita@ti.com>
* | i2c: omap: avoid reading interrupt enable registerVikram Pandita2011-09-161-3/+1
| | | | | | | | | | | | | | | | dev->iestate variable has the correct info on the interrupts enabled at any time. So avoid un-necessary I2C_IE_REG read. Change-Id: I75e315ef51b3f30bb41680cda7f4921218458fc1 Signed-off-by: Vikram Pandita <vikram.pandita@ti.com>
* | i2c: omap: cleanup interrupt enable logicVikram Pandita2011-09-161-18/+13
| | | | | | | | | | | | | | | | | | | | For omap4xxx do not use the legacy register I2C_IE, instead use the IRQENABLE_SET/CLR variant for future compatibility Also at probe, there is no need to enable interrupts. Change-Id: I103ce3c28a8a6d47a1a166cde440e73e772b2af2 Signed-off-by: Vikram Pandita <vikram.pandita@ti.com>
* | i2c: omap: fix clearing of int for omap44xxVikram Pandita2011-09-161-1/+1
| | | | | | | | | | | | | | IRQENABLE_CLR register should be written all 1's to clear interrupt enable Change-Id: I04298218d381726892646112c9130ffed982ad7f Signed-off-by: Vikram Pandita <vikram.pandita@ti.com>
* | i2c: omap: add omap4xxx irq status registerVikram Pandita2011-09-161-0/+2
| | | | | | | | | | | | | | No new functionality, just add the missing register Change-Id: I535e8a52f4bd12c9cea04db8f860ad82d85eedc9 Signed-off-by: Vikram Pandita <vikram.pandita@ti.com>
* | i2c: fix compile break when debug enabledVikram Pandita2011-09-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix this compile break when enable debug or compile with omap2plus_defconfig: drivers/i2c/i2c-core.c: In function 'i2c_detect_ext_master': drivers/i2c/i2c-core.c:1155: error: initializer element is not constant drivers/i2c/i2c-core.c:1155: error: (near initialization for 'descriptor.format') drivers/i2c/i2c-core.c:1155: warning: passing argument 2 of 'dev_printk' from incompatible pointer type include/linux/device.h:788: note: expected 'const struct device *' but argument is of type 'char *' make[2]: *** [drivers/i2c/i2c-core.o] Error 1 Change-Id: I9648c3d4a5f420cf71544b567ec58f49323abe7e Signed-off-by: Vikram Pandita <vikram.pandita@ti.com>
* | OMAP4: Provide handling of I2C channel controlled outside the mpuGilles-Arnaud Bleu-Laine2011-09-072-6/+75
| | | | | | | | | | | | | | | | Note: Perform some special handling for externally controlled I2C devices. For now we only disable spurious IRQs. Change-Id: I50731ca50d675b7a997b1c0f87797eb8a90bbc8c Signed-off-by: Gilles-Arnaud Bleu-Laine <gilles@ti.com>
* | Merge commit 'v3.0-rc7' into linux-omap-3.0Colin Cross2011-07-123-6/+17
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| * Merge branch 'for-30-rc5/all-i2c' of git://git.fluff.org/bjdooks/linuxLinus Torvalds2011-07-073-6/+17
| |\ | | | | | | | | | | | | | | | | | | | | | * 'for-30-rc5/all-i2c' of git://git.fluff.org/bjdooks/linux: i2c-bfin-twi: abort transfer is MEM bit is reset unexpectedly i2c-s3c2410: Remove useless break code i2c-s3c2410: Fix typo 'i2s' -> 'i2c' i2c: tegra: Assign unused slave address
| | *-. Merge branches 'for-30-rc4/i2c-bfin', 'for-30-rc4/i2c-omap', ↵Ben Dooks2011-06-272-5/+10
| | |\ \ | | | | | | | | | | | | | | | 'for-30-rc4/i2c-s3c' and 'for-30-rc4/i2c-tegra' into for-30-rc5/all-i2c
| | | | * i2c: tegra: Assign unused slave addressStephen Warren2011-06-271-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Tegra, we should always use the "new" I2C slave controller, to avoid issues with the old controller. This was implemented in commit 65a1a0a "i2c: tegra: Enable new slave mode." There is currently no driver for the Tegra I2C slave controller upstream. Additionally, the controller cannot be completely disabled. Instead, we need to: a) Set I2C_SL_CNFG_NACK to make the controller automatically NACK any incoming transactions. b) The controller's definition of NACK isn't identical to the I2C protocol's definition. Specifically, it will perform a standard NACK, but *also* continue to hold the clock line low in expectation of receiving more data. This can hang the bus, or at least cause transaction timeouts, if something starts a transaction that matches the controller's slave address. Since the default address is 0x00, the general call address, this does occur in practice. To avoid this, we explicitly program a slave address that is reserved for future expansion. For current boards, this guarantees the address will never be used. If a future board ever needs to use this address, we can add platform data to determine a board-specific safe address. 0xfc is picked by this patch. This patch is based on a change previously posted by: Wei Ni <wni@nvidia.com> http://www.spinics.net/lists/linux-i2c/msg05437.html In turned based on internal changes by: Bharat Nihalani <bnihalani@nvidia.com> A semantically equivalent change has been contained in the various ChromeOS kernels for a while. I tested this change on top of 3.0-rc2 on Harmony, and interacted with the WM8903 I2C-based audio codec. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
| | | * | i2c-s3c2410: Remove useless break codeJonghwan Choi2011-06-271-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
| | | * | i2c-s3c2410: Fix typo 'i2s' -> 'i2c'Huisung Kang2011-06-271-3/+3
| | | |/ | | | | | | | | | | | | | | | | | | | | Signed-off-by: Huisung Kang <hs1218.kang@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
| | * | i2c-bfin-twi: abort transfer is MEM bit is reset unexpectedlySonic Zhang2011-06-271-1/+7
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sometimes, the first I2C transmit interrupt is not serviced in time (like when higher priority interrupts take too long). Since the RESTART bit is not set before the next I2C clock, when the TWI handler is finally called, the I2C session is aborted (MEM bit is reset) and both SMITSERV and MCOMP int status bits are set. So when this happens, abort the transfer. Reported-by: Isabelle Leonardi <i.leonardi@detracom.fr> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
* | | Merge commit 'v3.0-rc6' into linux-omap-3.0Colin Cross2011-07-112-7/+8
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| * | i2c/pca954x: Initialize the mux to disconnected statePetri Gynther2011-06-291-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pca954x power-on default is channel 0 connected. If multiple pca954x muxes are connected to the same physical I2C bus, the parent bus will see channel 0 devices behind both muxes by default. This is bad. Scenario: -- pca954x @ 0x70 -- ch 0 (I2C-bus-101) -- EEPROM @ 0x50 | I2C-bus-1 --- | -- pca954x @ 0x71 -- ch 0 (I2C-bus-111) -- EEPROM @ 0x50 1. Load I2C bus driver: creates I2C-bus-1 2. Load pca954x driver: creates virtual I2C-bus-101 and I2C-bus-111 3. Load eeprom driver 4. Try to read EEPROM @ 0x50 on I2C-bus-101. The transaction will also bleed onto I2C-bus-111 because pca954x @ 0x71 channel 0 is connected by default. Fix: Initialize pca954x to disconnected state in pca954x_probe() Signed-off-by: Petri Gynther <pgynther@google.com> Signed-off-by: Jean Delvare <khali@linux-fr.org> Cc: stable@kernel.org
| * | i2c-taos-evm: Fix log messagesJean Delvare2011-06-291-4/+4
| |/ | | | | | | | | | | | | | | | | * Print all error and information messages even when debugging is disabled. * Don't use adapter device to log messages before it is ready. Signed-off-by: Jean Delvare <khali@linux-fr.org> Cc: stable@kernel.org
* | i2c-omap: OMAP4: PM: (re)init for every transfer to support off-modeRajendra Nayak2011-07-061-2/+2
| | | | | | | | | | | | | | | | Make sure the i2c registers are reinited on OMAP4 as its needed to support OFF mode. This was earlier only done on OMAP3 platform. Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
generated by cgit v1.1 at 2024-10-31 22:12:16 +0000