| Commit message (Collapse) | Author | Age | Files | Lines |
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Make certain we don't call pm_qos_remove_request if we have never
added the request in the first place as it produces a nasty looking
error message and stack track in the kernel logs.
Change-Id: I1e955f15944908706f3a67cf6be0603478036ea5
Signed-off-by: John Grossman <johngro@google.com>
Signed-off-by: Ruslan Bilovol <ruslan.bilovol@ti.com>
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Issue with entering blaze to suspend state fixed.
Also fixed error during hdmi driver resume when actual
hdmi device was not connected.
Change-Id: Iffb151982f020afb40dc2b39b35aa80a03091b32
Signed-off-by: Andrii Guriev <x0160204@ti.com>
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This change implements MEM2MEM mode for pannels blanked case.
Change-Id: Ic030682e7aaa33dd596d5150da23ab9dc1fc20f7
Signed-off-by: Artem Rudenko <artemrudenko@ti.com>
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Move taps selection logic before scaling check, so 3- of 5-tap always
get selected, no metter whether we do scaling or not.
Change-Id: I284b29933ca9fd69ae2088f279554dab9a66542c
Signed-off-by: Sergiy Kibrik <sergiy.kibrik@globallogic.com>
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In a current codebase L3 BW constraint is set if
any display has resution higher or equal FullHD.
Estimated available DSS bandwidth on L3@OPP50 is ~800MB/s.
It is approximately 3 WXGA layers or almost 1.5 FullHD layers at
60fps rate.
This patch relaxes L3 BW constraint and set it only
if current overlays' configuration needs higher BW.
Change-Id: I45afe36876e9898b45e20901d2b5c2633f32b914
Signed-off-by: Taras Kondratiuk <taras@ti.com>
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Before enabling pixel clock DSS should set its OPP
for OPP framework to set correct VDD_CORE voltage level.
When pixel clock is disabled DSS can set the lowest OPP.
Change-Id: Ia1459614ae306dba9b048b149e474442e2880bba
Signed-off-by: Taras Kondratiuk <taras@ti.com>
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Pass correct arguments to FIR filter selection. Previously we
always ended up selecting M19 5-tap filter.
This should improve image quality of scaled layers.
Change-Id: Iabe3219df7dcfd62c713fd92ee9c3d12221bc382
Signed-off-by: Lajos Molnar <lajos@ti.com>
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This change adds capability to activate HDMI connection if
cable was plugged in during suspend mode.
Change-Id: I3f17489f16a3157fe20ae4ab86b4964a672f595f
Signed-off-by: Mykhailo Denysiuk <x0172934@ti.com>
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Report HDMI as manually updated panel. Currently it is
default treated as auto updated panel by OMAPFB.
This is used by OMAPFB to determine if VSYNC notification
is possible by panel or not.
Change-Id: I3d1fe91f79fd2a39497bea700f9653ef141b310f
Signed-off-by: Muralidhar Dixit <murali.dixit@ti.com>
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p-android-omap-3.0-dev
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Use division with rounding-up when checking if maximum downscale ratio
was reached. This allows to avoid SYNC_LOST errors in case when small
amount of extra pixels or lines (usually 1-3) not taken into account
Change-Id: Id8f88c64671146a64738cfd820378bb7a28c1455
Signed-off-by: Sergiy Kibrik <sergiy.kibrik@globallogic.com>
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Changing the CEC event to avoid conflict with HDMI
event
Change-Id: I08748e6a7b2879ffec12f009afb8b03522247309
Signed-off-by: Muralidhar Dixit <murali.dixit@ti.com>
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Added get_resolution and get_fb_resolution function to HDMI
driver so that we can configure defaults via board files when
HDMI is default panel.
Change-Id: I36cafb4b0bd42c150c1c1a03be4607edec31b4db
Co-Author-by: Victor Kleinik <x0150886@ti.com>
Co-Author-by: Artem Rudenko <artemrudenko@ti.com>
Signed-off-by: Dandawate Saket <dsaket@ti.com>
Signed-off-by: Muralidhar Dixit <murali.dixit@ti.com>
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This is a workaround that prevents SYNC_LOST on changing pipe
channelout from manager which was used as a source of wb to
another manager. Manager could free pipes after wb will
send SYNC message but that will start wb capture. To prevent
that we reconnect the pipe from the manager to wb and do a
dummy enabling and disabling of wb - the pipe will be freed
and capture won't start because source pipe is switched off.
Change-Id: Ib4cfbb1854c92a2e507589fbe8cf00e5cb6831ca
Signed-off-by: Artem Rudenko <x0150883@ti.com>
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This change fixes black frames issue in MEM2MEM mode.
The root of the problem is in apply_irq_handler function, which
time-to-time is called between calls to omap_dss_wb_apply() and
omap_dss_mgr_apply() functions. So, apply_irq_handler sometimes
is called when WB cache was updated, but managr cache and others
caches were not updated yet.
Change-Id: I308f5ef7d7b6e790382c22c40b8cddedaf91308e
Signed-off-by: Rohit Choraria <rohitkc@ti.com>
Signed-off-by: Mykhailo Denysiuk <x0172934@ti.com>
Signed-off-by: Sergiy Kibrik <sergiy.kibrik@globallogic.com>
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This change adds workaround for errata i642.
Description of Errata i642:
VID /GFX Pipeline Underflow Interrupt Generated When In WB
Memory-to-memory Operation. Errata ID: i642.
Recommended workaround:
Software should disable the VID/GFX pipeline underflow interrupt
by writing 0x0 in DISPC_IRQENABLE[20-12-10-6] bit if it is
connected to the WB pipeline in memory-to-memory mode.
Software should not consider the underflow interrupt generated in
DISPC_IRQSTATUS[20-12-10-6] bit when in memory-to-memory mode.
This change do not disable interrupt, but ignores its handler in
case if pipeline connected to the manager, which is used in MEM2MEM
mode.
Silicon Versions Impacted:
OMAP4430 ES1.0, ES2.0, ES2.1, ES2.2, ES2.3
OMAP4460 ES1.0, ES1.1
OMAP4470 ES1.0
Change-Id: If7532b1b7454d92a648673b6da29cc31448519ab
Author: Rohit Choraria <rohitkc@ti.com>
Co-author: Mykhailo Denysiuk <x0172934@ti.com>
Signed-off-by: Mykhailo Denysiuk <x0172934@ti.com>
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This change adds memory-to-memory (M2M) mode with using of the
manager. The main idea is to connect write back (WB) pipeline to
the manager (overlay, in terms of technical reference manual)
which is not in use (physical interface is turned-off) for using
advantages of hardware manager in M2M mode. In this case several
pipelines can be connected to the manager.
Change-Id: Ifa649bd5b18f54f3ce583fdee802c799b2c30711
Co-author: Sergiy Kibrik <sergiikibrik@ti.com>
Signed-off-by: Mykhailo Denysiuk <x0172934@ti.com>
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This patch prevents skipping of frames in case we setup
a new composition until WB finishes the previous one.
Change-Id: I5793dec7f0856ce94674f326383de59f935a2f07
Signed-off-by: Artem Rudenko <artemrudenko@ti.com>
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manual mode
Description: Upon errors returned from configure_dispc for manually
updated panels in dss_setup_partial_planes, previous compositions
needs to be cleared to ensure SGX won't block on commandcomplete
function indefinitely.
This patch depends on http://review.omapzoom.org/#/c/20659/
Can not be merged without it.
Change-Id: Id125a7a7d83e317af868472ba62297b7673ccb47
Signed-off-by: Kostiantyn Luzan <x0166170@ti.com>
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According to TRM, the HDMI_TXPHY_TX_CONTROL.FREQOUT bit has to be programmed
based on the clock frequency. But this bit is always programmed as 1 in the HDMI
driver irrespective of the clock frequency values. Fix this and program
HDMI_TXPHY_TX_CONTROL.FREQOUT based on the clock frequency.
Change-Id: I25a4c335ec773e241cc0daca5c1c1c8f223cd4a0
Signed-off-by: TAKAHASHI, Masato <m_takahashi@ti.com>
Signed-off-by: Varadarajan, Charulatha <charu@ti.com>
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Kernel version updated to 3.0.31
Change-Id: Ifbd7150801f3beeec9cbaa566f249d8019ef9348
Signed-off-by: Roman Shaposhnikov <x0166637@ti.com>
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This is a workaround. According to TRM we should disable the manager
but it will cause blinking of panel. WA is to disable pipe which was
used as source of WB and do dummy enable and disable of WB.
Change-Id: Ie1834fcef10b1cee98522c4251e771447760b9f3
Signed-off-by: Artem Rudenko <artemrudenko@ti.com>
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When WB captures from an overlay in MEM2MEM mode, the captured
image may be up-scaled beyond the size of the display.
Change-Id: Idac2c5082fb60d68d996c15daf8a13080b1f068e
Signed-off-by: Mykola Ostrovskyy <mykola@ti.com>
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Support for Memory-to-Memory writeback mode for capturing from pipes.
Change-Id: I8bc3b62f12aaafbfd0771ee6fe3d3ce84421a19e
Signed-off-by: Artem Rudenko <artemrudenko@ti.com>
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Request higher L3 bandwidth when we have 1080p, or higher,
resolution framebuffer. This is done to avoid underflow on
DSS pipelines.
Change-Id: Ieca56ae8bc9ec6147ab9301c267c29279a9399ca
Signed-off-by: Dandawate Saket <dsaket@ti.com>
Signed-off-by: Peter Nordström <nordstrom@ti.com>
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Change-Id: I695b59aeccd2e5cb5a50c6fc734c5d54795f5615
Signed-off-by: Dima Svetlov <svetlov@ti.com>
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panels"
This reverts commit 1fe611b1c2eea594ed3738d50bfb37a701d2632c.
Change-Id: I444e0e09a99ce5f495ffc298d388678e0e07cda4
Signed-off-by: Dima Svetlov <svetlov@ti.com>
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As per the simultaion team suggestion, the below thesholds are set:
HT = fifosize * 5/8;
LT = fifosize * 4/8;
Change-Id: Ieef7d8a090e38ce717729fe30f60f46c6dfd6ddd
Signed-off-by: Sunita Nadampalli <sunitan@ti.com>
Signed-off-by: Lajos Molnar <lajos@ti.com>
Signed-off-by: Dima Svetlov <svetlov@ti.com>
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DSI and DISPC parameters cannot always be calculated by the
driver, so add fields to allow for providing detailed
configuration from the board file.
Change-Id: If8ad5c7c6479ae221b5dd8ddd44d845ab5756974
Signed-off-by: Peter Nordström <nordstrom@ti.com>
Signed-off-by: Lajos Molnar <lajos@ti.com>
Signed-off-by: Dima Svetlov <svetlov@ti.com>
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According to TRM, minimal pixel clock divisor value can be 1.
Fix corresponding checks, as high resolution panels use undivided
pixel clock frequency.
Also certain scaler unit constraint must be met: in case DISPC_CLK
and pixel clock frequencies are equal, set IPC to work on rising edge.
Change-Id: Iabeac2ad81f6909213cb81f4e16b1d0762369b53
Signed-off-by: Sergiy Kibrik <sergiy.kibrik@globallogic.com>
Signed-off-by: Lajos Molnar <lajos@ti.com>
Signed-off-by: Dima Svetlov <svetlov@ti.com>
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OMAP44xx has hardware limitation: in stall mode, when the frame pixel size
is less than output SyncFifo depth(16), DISPC hangs without sending any data.
Simple workaround is to drop such frame, as cases when YUV frames of this size
are very rare.
Change-Id: I31dc262b07a52b66209c093f136ad2bac66f9439
Signed-off-by: Sergiy Kibrik <sergiy.kibrik@globallogic.com>
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Adding support for CEC key board driver in input device.
UI commands received from CEC are mapped to the key buttons
in the linux kernel.
Change-Id: If4136940f28fb4a0c4b9b730aabb8e0fc7837ccf
Signed-off-by: Muralidhar Dixit <murali.dixit@ti.com>
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Adding CEC driver support in HDMI
Change-Id: Ia6a7d04b1df3a459ae435f8bec79219b2036dfa0
Signed-off-by: Muralidhar Dixit <murali.dixit@ti.com>
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Adding support for call back from HDMI to CEC driver
on HPD and HDMI enable.
Change-Id: I9fff9d41d598e5ef375bc03faafb9a559ce7435a
Signed-off-by: Muralidhar Dixit <murali.dixit@ti.com>
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HDMI sink device will set the physical address for
CEC devices
Change-Id: I6419834816978dfc8bcb8ef9a7b6c36276e5792c
Signed-off-by: Muralidhar Dixit <murali.dixit@ti.com>
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The current design does not work correctly in case when we are using large
panels with 1080p resolution as default. It happens because current fclk rate
is less then required one. This patch corrects that issue by increasing
PLL1_CLK1 frequency. Also it removes excess initialization of the DISPC fclk
src from HDMI driver.
Change-Id: I24cdbfc417034a9275b1f305a8754bbae306da48
Signed-off-by: Victor Kleinik <x0150886@ti.com>
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Port write back support from 2.6.35.
Support for mem2mem mode with overlay/mgr as
input will be added later.
Change-Id: I17efea1d9897f8f9cd2ed8f9623198e0a63c8fba
Signed-off-by: Mythri P K <mythripk@ti.com>
Signed-off-by: Rohit Choraria <rohitkc@ti.com>
Signed-off-by: Sreenidhi Koti <sreenidhi@ti.com>
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Routine names in debug messages of dsi_vc_gen_read_2() and dsi_vc_dcs_read()
are set to same "dsi_vc_rcs_read". Fix routine names in these messages.
Change-Id: I9cceca5711932ba2c2ea3f2919baf461e30ddd8b
Signed-off-by: Sergiy Kibrik <sergiy.kibrik@globallogic.com>
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This patch enables MFLAG support for OMAP4470 SOCs.
MFLAG changes the arbitration on L3, so DMA of DSS will read
a frame data with a high priority. This is important for
high resolution displays like 1080p and above.
Change-Id: I7e058ec52068bc0c37a6152a6656a90ec3194706
Signed-off-by: Artem Rudenko <artemrudenko@ti.com>
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This reverts commit 0e11c5b311d2c7436756f80c35c8aef4cd0d911b.
The SW workaround is no longer needed as a hardware workaround
exists, and the SW workaround created artifacts.
Change-Id: I5d8a601b24502a3ac5d4c1f17fcb3936ba8e7e10
Signed-off-by: Sathya Prakash M R <a0393677@ti.com>
Signed-off-by: Lajos Molnar <lajos@ti.com>
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vidrot attribute is ignored for NV12 format, but setting it to
1 prevents overread of the UV plane when scaling.
Change-Id: If436c26aace4c805723ccfc1bd2b989bdc7efcd5
Signed-off-by: Sathya Prakash M R <a0393677@ti.com>
Signed-off-by: Lajos Molnar <lajos@ti.com>
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Display driver logic to calculate the recommended bpp for FB has been modified
to recommend 24bit for all panels above 16bit mode.
DRT# OMAPS00259536 - ICS R0: App Tray disappears on Hi Res display (1920x1200)
Change-Id: I16aad396083d0ad416e035c59a93089df20d6d82
Signed-off-by: Sunita Nadampalli <sunitan@ti.com>
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This change is to bypass the wait_for_audio_stop loop if turning off
hdmi for resync after resume while playing audio.
This fixes slow system response and the delay in the return of
audio after resume.
OMAPS00260109 Device will become slow if you play music with HDMI
while wakeup from suspend.
Change-Id: I1dec017fbbe117604885fab1dddbe8411b2844d2
Signed-off-by: Bryan Honza <honza@ti.com>
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Calculation of bytes per pixel in dispc_to_dsi_clock() is not precise,
based on static value definition.
Instead, it should be calculated in-place, based on actual pixel size,
which produce more accurate numbers in situations where remainder appears
(e.g. 18-bit pixel size).
Change-Id: I4c90b2ec5e1d6139d84cbdc55af3f2a484785968
Signed-off-by: Sergiy Kibrik <sergiy.kibrik@globallogic.com>
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Conflicts:
arch/arm/mach-omap2/Kconfig
arch/arm/mach-omap2/omap_twl.c
drivers/mmc/host/omap_hsmmc.c
drivers/usb/gadget/android.c
drivers/video/hdmi_ti_4xxx_ip.c
drivers/video/omap2/dss/hdmi.c
fs/proc/base.c
include/video/hdmi_ti_4xxx_ip.h
sound/soc/codecs/twl6040.c
sound/soc/omap/sdp4430.c
Signed-off-by: Dan Murphy <dmurphy@ti.com>
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It has been identified that in addition to L3_1, L3_2 clock domain is
also suspetible to the erratum (erratum ID is pending) described below.
Issue: Mstandby and disconnect protocol issue
impacts: all OMAP4 devices
Simplfied Description:
issue #1: The handshake between IP modules on L3_1 and L3_2 peripherals with
PRCM has a limitation in a certain time window of L4 clock cycle. Due to the
fact that a wrong variant of stall signal was used in circuit of PRCM, the
intitator-interconnect protocol is broken when the time window is hit where
the PRCM requires the interconnect to go to idle while intitator asks to
wakeup.
Issue #2: DISPC asserts a sub-mstandby signal for a short period. In this
time interval, IP block requests disconnection of Master port, and results
in Mstandby and wait request to PRCM. In parallel, if mstandby is de-asserted
by DISPC simultaneously, interconnect requests for a reconnect for one cycle
alone resulting in a disconnect protocol violation and a deadlock of the
system.
Workaround:
L3_1 clock domain must not be programmed in HW_AUTO if
Static dependency with DSS is enabled and DSS clock domain
is ON. Same for L3_2.
Patch with changeID I28ae362ad330a79a493927575c9570462c4303a7
(omap: dispc: force L3_1 CD to NOSLEEP when dispc module is active)
already introduces the work around for L3_1. Here we add L3_2
clock domain as well + update the comments and wrap the WA under
an OMAP4 flag.
Change-Id: I476eedbac34e1876d413a15a524c3b4bb3732b9f
Signed-off-by: Akash Choudhari <akashc@ti.com>
Signed-off-by: Mahesh Renduchintala <mahesh@ti.com>
CC: Todd Poynor <toddpoynor@google.com>
CC: Colin Cross <ccross@android.com>
CC: Nishanth Menon <nm@ti.com>
CC: Girish S G <girishsg@ti.com>
CC: Dandawate Saket <dsaket@ti.com>
CC: Lajos Molnar <molnar@ti.com>
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When AKSV values loaded in HDCP key memory are incorrect,
do not perform HDCP authentication.
Change-Id: Ia4f5890df9e2beb0e754331021aa4693c51d9443
Signed-off-by: Srinivas Pulukuru <srinivas.pulukuru@ti.com>
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With the DSS FIFO optimizations, ramdom lockups and reboots are seen. It has
been identified that L3_1 CD is idling and not responding to the traffic
initiated by DSS. The Workaround suggested by Hardware team is to keep the
L3_1 CD in NO_SLEEP mode, when DSS is active. Once DSS module is switched to
idle mode, put L3_1 CD to HW_AUTO.
Change-Id: I28ae362ad330a79a493927575c9570462c4303a7
Signed-off-by: Akash Choudhari <akashc@ti.com>
Signed-off-by: Avinash.H.M. <avinashhm@ti.com>
Signed-off-by: Sunita Nadampalli <sunitan@ti.com>
CC: Todd Poynor <toddpoynor@google.com>
CC: Colin Cross <ccross@android.com>
CC: Nishanth Menon <nm@ti.com>
CC: Girish S G <girishsg@ti.com>
CC: Mahesh <mahesh@ti.com>
CC: Dandawate Saket <dsaket@ti.com>
CC: Lajos Molnar <molnar@ti.com>
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During the initialization of DSI,some times BTA
sent by OMAP DSI, was not receiving an BTA ACK.
To rectify this, we need to reset the DSI module
whenever we diable-enable the DSI module.
Change-Id: Ic2542970da06a121559a8cc700222881c60c025c
Signed-off-by: Sujeet Kumar Baranwal <s-baranwal@ti.com>
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