diff options
author | Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> | 2007-03-05 19:10:03 +0900 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2007-04-27 16:20:23 +0100 |
commit | 2a9effc67804102d6d5182eb0116520588ae2256 (patch) | |
tree | 7ae021afd779f245050907fbab76c2e555491889 /arch/mips/cobalt/pci.c | |
parent | cc50b67dcd84c6215232c0e1c95e24786e555782 (diff) | |
download | kernel_samsung_smdk4412-2a9effc67804102d6d5182eb0116520588ae2256.zip kernel_samsung_smdk4412-2a9effc67804102d6d5182eb0116520588ae2256.tar.gz kernel_samsung_smdk4412-2a9effc67804102d6d5182eb0116520588ae2256.tar.bz2 |
[MIPS] Cobalt: Split PCI codes from setup.c
It's removed #ifdef CONFIG_PCI/#endif from cobalt setup.c .
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/cobalt/pci.c')
-rw-r--r-- | arch/mips/cobalt/pci.c | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/arch/mips/cobalt/pci.c b/arch/mips/cobalt/pci.c new file mode 100644 index 0000000..d016006 --- /dev/null +++ b/arch/mips/cobalt/pci.c @@ -0,0 +1,47 @@ +/* + * Register PCI controller. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996, 1997, 2004, 05 by Ralf Baechle (ralf@linux-mips.org) + * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv) + * + */ +#include <linux/init.h> +#include <linux/pci.h> + +#include <asm/gt64120.h> + +extern struct pci_ops gt64111_pci_ops; + +static struct resource cobalt_mem_resource = { + .start = GT_DEF_PCI0_MEM0_BASE, + .end = GT_DEF_PCI0_MEM0_BASE + GT_DEF_PCI0_MEM0_SIZE - 1, + .name = "PCI memory", + .flags = IORESOURCE_MEM, +}; + +static struct resource cobalt_io_resource = { + .start = 0x1000, + .end = GT_DEF_PCI0_IO_SIZE - 1, + .name = "PCI I/O", + .flags = IORESOURCE_IO, +}; + +static struct pci_controller cobalt_pci_controller = { + .pci_ops = >64111_pci_ops, + .mem_resource = &cobalt_mem_resource, + .io_resource = &cobalt_io_resource, + .io_offset = 0 - GT_DEF_PCI0_IO_BASE, +}; + +static int __init cobalt_pci_init(void) +{ + register_pci_controller(&cobalt_pci_controller); + + return 0; +} + +arch_initcall(cobalt_pci_init); |