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| author | Atsushi Nemoto <anemo@mba.ocn.ne.jp> | 2007-01-08 02:14:29 +0900 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2007-02-06 16:53:08 +0000 |
| commit | 97dcb82de6cc99a5669eb8e342efc24cceb1e77e (patch) | |
| tree | e195fd57deda8d38652c746c04a7c374cdf951a0 /arch/mips/ddb5xxx | |
| parent | b6ec8f069bf202d2bd888aa9137b2cc3aad4c573 (diff) | |
| download | kernel_samsung_smdk4412-97dcb82de6cc99a5669eb8e342efc24cceb1e77e.zip kernel_samsung_smdk4412-97dcb82de6cc99a5669eb8e342efc24cceb1e77e.tar.gz kernel_samsung_smdk4412-97dcb82de6cc99a5669eb8e342efc24cceb1e77e.tar.bz2 | |
[MIPS] Define MIPS_CPU_IRQ_BASE in generic header
The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all
platforms and are same value on most platforms (0 or 16, depends on
CONFIG_I8259). Define them in asm-mips/mach-generic/irq.h and make
them customizable. This will save a few cycle on each CPU interrupt.
A good side effect is removing some dependencies to MALTA in generic
SMTC code.
Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq
mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing
them might cause some header dependency problem and there seems no
good reason to customize it. So currently only VR41XX is using custom
MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259.
Testing this patch on those platforms is greatly appreciated. Thank
you.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/ddb5xxx')
| -rw-r--r-- | arch/mips/ddb5xxx/ddb5477/irq.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/ddb5xxx/ddb5477/irq.c b/arch/mips/ddb5xxx/ddb5477/irq.c index a8bd2e6..bd7cd7c 100644 --- a/arch/mips/ddb5xxx/ddb5477/irq.c +++ b/arch/mips/ddb5xxx/ddb5477/irq.c @@ -17,6 +17,7 @@ #include <linux/ptrace.h> #include <asm/i8259.h> +#include <asm/irq_cpu.h> #include <asm/system.h> #include <asm/mipsregs.h> #include <asm/debug.h> @@ -73,7 +74,6 @@ set_pci_int_attr(u32 pci, u32 intn, u32 active, u32 trigger) } extern void vrc5477_irq_init(u32 base); -extern void mips_cpu_irq_init(u32 base); static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL }; void __init arch_init_irq(void) @@ -125,7 +125,7 @@ void __init arch_init_irq(void) /* init all controllers */ init_i8259_irqs(); - mips_cpu_irq_init(CPU_IRQ_BASE); + mips_cpu_irq_init(); vrc5477_irq_init(VRC5477_IRQ_BASE); |