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author | Linus Torvalds <torvalds@linux-foundation.org> | 2008-10-11 11:47:30 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2008-10-11 11:51:16 -0700 |
commit | ead9d23d803ea3a73766c3cb27bf7563ac8d7266 (patch) | |
tree | 42225fadd0d5388bf21d1658e56879e14f23e013 /arch/x86/mach-default/setup.c | |
parent | bf6f51e3a46f6a602853d3cbacd05864bc6e2a37 (diff) | |
parent | 0afe2db21394820d32646a695eccf3fbfe6ab5c7 (diff) | |
download | kernel_samsung_smdk4412-ead9d23d803ea3a73766c3cb27bf7563ac8d7266.zip kernel_samsung_smdk4412-ead9d23d803ea3a73766c3cb27bf7563ac8d7266.tar.gz kernel_samsung_smdk4412-ead9d23d803ea3a73766c3cb27bf7563ac8d7266.tar.bz2 |
Merge phase #4 (X2APIC, APIC unification, CPU identification unification) of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'x86-v28-for-linus-phase4-D' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (186 commits)
x86, debug: print more information about unknown CPUs
x86 setup: handle more than 8 CPU flag words
x86: cpuid, fix typo
x86: move transmeta cap read to early_init_transmeta()
x86: identify_cpu_without_cpuid v2
x86: extended "flags" to show virtualization HW feature in /proc/cpuinfo
x86: move VMX MSRs to msr-index.h
x86: centaur_64.c remove duplicated setting of CONSTANT_TSC
x86: intel.c put workaround for old cpus together
x86: let intel 64-bit use intel.c
x86: make intel_64.c the same as intel.c
x86: make intel.c have 64-bit support code
x86: little clean up of intel.c/intel_64.c
x86: make 64 bit to use amd.c
x86: make amd_64 have 32 bit code
x86: make amd.c have 64bit support code
x86: merge header in amd_64.c
x86: add srat_detect_node for amd64
x86: remove duplicated force_mwait
x86: cpu make amd.c more like amd_64.c v2
...
Diffstat (limited to 'arch/x86/mach-default/setup.c')
-rw-r--r-- | arch/x86/mach-default/setup.c | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/arch/x86/mach-default/setup.c b/arch/x86/mach-default/setup.c index 3f2cf11..37b9ae4 100644 --- a/arch/x86/mach-default/setup.c +++ b/arch/x86/mach-default/setup.c @@ -38,15 +38,6 @@ void __init pre_intr_init_hook(void) init_ISA_irqs(); } -/* - * IRQ2 is cascade interrupt to second interrupt controller - */ -static struct irqaction irq2 = { - .handler = no_action, - .mask = CPU_MASK_NONE, - .name = "cascade", -}; - /** * intr_init_hook - post gate setup interrupt initialisation * @@ -62,12 +53,6 @@ void __init intr_init_hook(void) if (x86_quirks->arch_intr_init()) return; } -#ifdef CONFIG_X86_LOCAL_APIC - apic_intr_init(); -#endif - - if (!acpi_ioapic) - setup_irq(2, &irq2); } /** |