diff options
| author | Anton Blanchard <anton@samba.org> | 2005-09-06 14:52:12 +1000 |
|---|---|---|
| committer | Paul Mackerras <paulus@samba.org> | 2005-09-06 16:09:21 +1000 |
| commit | a6908cd00036080fbea14ff67335e5f2a1ab5489 (patch) | |
| tree | 8ec2f5c877d9f1392184cfd31921cab7a5392c4b /arch | |
| parent | 8530935d384bef1467ba76e1f4382f0f8b3c899d (diff) | |
| download | kernel_samsung_smdk4412-a6908cd00036080fbea14ff67335e5f2a1ab5489.zip kernel_samsung_smdk4412-a6908cd00036080fbea14ff67335e5f2a1ab5489.tar.gz kernel_samsung_smdk4412-a6908cd00036080fbea14ff67335e5f2a1ab5489.tar.bz2 | |
[PATCH] ppc64: Use num_pmcs in oprofile code
Change oprofile to use num_pmcs from the cpu feature struct.
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/ppc64/oprofile/common.c | 7 | ||||
| -rw-r--r-- | arch/ppc64/oprofile/op_model_power4.c | 9 |
2 files changed, 5 insertions, 11 deletions
diff --git a/arch/ppc64/oprofile/common.c b/arch/ppc64/oprofile/common.c index 4acd1a4..a376eb2 100644 --- a/arch/ppc64/oprofile/common.c +++ b/arch/ppc64/oprofile/common.c @@ -16,6 +16,7 @@ #include <asm/ptrace.h> #include <asm/system.h> #include <asm/pmc.h> +#include <asm/cputable.h> #include "op_impl.h" @@ -131,7 +132,6 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) case PV_630: case PV_630p: model = &op_model_rs64; - model->num_counters = 8; ops->cpu_type = "ppc64/power3"; break; @@ -140,14 +140,12 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) case PV_ICESTAR: case PV_SSTAR: model = &op_model_rs64; - model->num_counters = 8; ops->cpu_type = "ppc64/rs64"; break; case PV_POWER4: case PV_POWER4p: model = &op_model_power4; - model->num_counters = 8; ops->cpu_type = "ppc64/power4"; break; @@ -155,14 +153,12 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) case PV_970FX: case PV_970MP: model = &op_model_power4; - model->num_counters = 8; ops->cpu_type = "ppc64/970"; break; case PV_POWER5: case PV_POWER5p: model = &op_model_power4; - model->num_counters = 6; ops->cpu_type = "ppc64/power5"; break; @@ -170,6 +166,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) return -ENODEV; } + model->num_counters = cur_cpu_spec->num_pmcs; ops->create_files = op_ppc64_create_files; ops->setup = op_ppc64_setup; ops->shutdown = op_ppc64_shutdown; diff --git a/arch/ppc64/oprofile/op_model_power4.c b/arch/ppc64/oprofile/op_model_power4.c index 3d103d6..e469610 100644 --- a/arch/ppc64/oprofile/op_model_power4.c +++ b/arch/ppc64/oprofile/op_model_power4.c @@ -23,7 +23,6 @@ static unsigned long reset_value[OP_MAX_COUNTER]; -static int num_counters; static int oprofile_running; static int mmcra_has_sihv; @@ -45,8 +44,6 @@ static void power4_reg_setup(struct op_counter_config *ctr, { int i; - num_counters = num_ctrs; - /* * SIHV / SIPR bits are only implemented on POWER4+ (GQ) and above. * However we disable it on all POWER4 until we verify it works @@ -68,7 +65,7 @@ static void power4_reg_setup(struct op_counter_config *ctr, backtrace_spinlocks = sys->backtrace_spinlocks; - for (i = 0; i < num_counters; ++i) + for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) reset_value[i] = 0x80000000UL - ctr[i].count; /* setup user and kernel profiling */ @@ -121,7 +118,7 @@ static void power4_start(struct op_counter_config *ctr) /* set the PMM bit (see comment below) */ mtmsrd(mfmsr() | MSR_PMM); - for (i = 0; i < num_counters; ++i) { + for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) { if (ctr[i].enabled) { ctr_write(i, reset_value[i]); } else { @@ -272,7 +269,7 @@ static void power4_handle_interrupt(struct pt_regs *regs, /* set the PMM bit (see comment below) */ mtmsrd(mfmsr() | MSR_PMM); - for (i = 0; i < num_counters; ++i) { + for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) { val = ctr_read(i); if (val < 0) { if (oprofile_running && ctr[i].enabled) { |