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author | Paul Mundt <lethal@linux-sh.org> | 2010-06-02 17:10:44 +0900 |
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committer | Paul Mundt <lethal@linux-sh.org> | 2010-06-02 17:10:44 +0900 |
commit | f4d7c3565c1692c54d9152b52090fe73f0029e37 (patch) | |
tree | 1bda3fdcdd3b706542f9464aed84d346fa5fab25 /drivers/clocksource | |
parent | 66f49121ffa41a19c59965b31b046d8368fec3c7 (diff) | |
download | kernel_samsung_smdk4412-f4d7c3565c1692c54d9152b52090fe73f0029e37.zip kernel_samsung_smdk4412-f4d7c3565c1692c54d9152b52090fe73f0029e37.tar.gz kernel_samsung_smdk4412-f4d7c3565c1692c54d9152b52090fe73f0029e37.tar.bz2 |
clocksource: sh_cmt: compute mult and shift before registration
Based on the sh_tmu change in 66f49121ffa41a19c59965b31b046d8368fec3c7
("clocksource: sh_tmu: compute mult and shift before registration").
The same issues impact the sh_cmt driver, so we take the same approach
here.
Cc: stable@kernel.org
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'drivers/clocksource')
-rw-r--r-- | drivers/clocksource/sh_cmt.c | 22 |
1 files changed, 13 insertions, 9 deletions
diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c index f6677cb..f3d3898 100644 --- a/drivers/clocksource/sh_cmt.c +++ b/drivers/clocksource/sh_cmt.c @@ -412,18 +412,10 @@ static cycle_t sh_cmt_clocksource_read(struct clocksource *cs) static int sh_cmt_clocksource_enable(struct clocksource *cs) { struct sh_cmt_priv *p = cs_to_sh_cmt(cs); - int ret; p->total_cycles = 0; - ret = sh_cmt_start(p, FLAG_CLOCKSOURCE); - if (ret) - return ret; - - /* TODO: calculate good shift from rate and counter bit width */ - cs->shift = 0; - cs->mult = clocksource_hz2mult(p->rate, cs->shift); - return 0; + return sh_cmt_start(p, FLAG_CLOCKSOURCE); } static void sh_cmt_clocksource_disable(struct clocksource *cs) @@ -450,8 +442,20 @@ static int sh_cmt_register_clocksource(struct sh_cmt_priv *p, cs->resume = sh_cmt_clocksource_resume; cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8); cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; + + /* clk_get_rate() needs an enabled clock */ + clk_enable(p->clk); + p->rate = clk_get_rate(p->clk) / (p->width == 16) ? 512 : 8; + clk_disable(p->clk); + + /* TODO: calculate good shift from rate and counter bit width */ + cs->shift = 10; + cs->mult = clocksource_hz2mult(p->rate, cs->shift); + dev_info(&p->pdev->dev, "used as clock source\n"); + clocksource_register(cs); + return 0; } |