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| author | Phil Sutter <phil.sutter@viprinet.com> | 2011-11-16 18:28:01 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2011-12-09 08:52:20 -0800 |
| commit | e84ce11bd0183328e00accb611893b9a819dc0ba (patch) | |
| tree | 88d22601f6032cacfa7ad227352c688b289748f9 /drivers/crypto | |
| parent | 4d15dcb0e249cd9834afc9b44d674dbd9eb57116 (diff) | |
| download | kernel_samsung_smdk4412-e84ce11bd0183328e00accb611893b9a819dc0ba.zip kernel_samsung_smdk4412-e84ce11bd0183328e00accb611893b9a819dc0ba.tar.gz kernel_samsung_smdk4412-e84ce11bd0183328e00accb611893b9a819dc0ba.tar.bz2 | |
crypto: mv_cesa - fix hashing of chunks > 1920 bytes
commit 274252862f386b7868f35bf5ceaa5391a8ccfdf3 upstream.
This was broken by commit 7759995c75ae0cbd4c861582908449f6b6208e7a (yes,
myself). The basic problem here is since the digest state is only saved
after the last chunk, the state array is only valid when handling the
first chunk of the next buffer. Broken since linux-3.0.
Signed-off-by: Phil Sutter <phil.sutter@viprinet.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/crypto')
| -rw-r--r-- | drivers/crypto/mv_cesa.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/drivers/crypto/mv_cesa.c b/drivers/crypto/mv_cesa.c index 3cf303e..38a3297 100644 --- a/drivers/crypto/mv_cesa.c +++ b/drivers/crypto/mv_cesa.c @@ -342,11 +342,13 @@ static void mv_process_hash_current(int first_block) else op.config |= CFG_MID_FRAG; - writel(req_ctx->state[0], cpg->reg + DIGEST_INITIAL_VAL_A); - writel(req_ctx->state[1], cpg->reg + DIGEST_INITIAL_VAL_B); - writel(req_ctx->state[2], cpg->reg + DIGEST_INITIAL_VAL_C); - writel(req_ctx->state[3], cpg->reg + DIGEST_INITIAL_VAL_D); - writel(req_ctx->state[4], cpg->reg + DIGEST_INITIAL_VAL_E); + if (first_block) { + writel(req_ctx->state[0], cpg->reg + DIGEST_INITIAL_VAL_A); + writel(req_ctx->state[1], cpg->reg + DIGEST_INITIAL_VAL_B); + writel(req_ctx->state[2], cpg->reg + DIGEST_INITIAL_VAL_C); + writel(req_ctx->state[3], cpg->reg + DIGEST_INITIAL_VAL_D); + writel(req_ctx->state[4], cpg->reg + DIGEST_INITIAL_VAL_E); + } } memcpy(cpg->sram + SRAM_CONFIG, &op, sizeof(struct sec_accel_config)); |