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authorCatalin Marinas <catalin.marinas@arm.com>2010-08-31 13:05:22 +0100
committerSantosh Shilimkar <santosh.shilimkar@ti.com>2010-10-26 11:39:54 +0530
commit9a6655e49fd98f3748bb80da20705448aad9ee57 (patch)
treedb5aba3a886712f54f4816137c4cea08b954f5c6 /drivers
parent899611ee7d373e5eeda08e9a8632684e1ebbbf00 (diff)
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ARM: Improve the L2 cache performance when PL310 is used
With this L2 cache controller, the cache maintenance by PA and sync operations are atomic and do not require a "wait" loop. This patch conditionally defines the cache_wait() function. Since L2x0 cache controllers do not work with ARMv7 CPUs, the patch automatically enables CACHE_PL310 when only CPU_V7 is defined. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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