diff options
Diffstat (limited to 'arch')
45 files changed, 476 insertions, 423 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 08c2ece..747a9c1 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -308,6 +308,7 @@ config MIPS_ATLAS select SYS_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_MULTITHREADING if EXPERIMENTAL help This enables support for the MIPS Technologies Atlas evaluation board. @@ -324,6 +325,7 @@ config MIPS_MALTA select I8259 select MIPS_BOARDS_GEN select MIPS_BONITO64 + select MIPS_CPU_SCACHE select MIPS_GT64120 select MIPS_MSC select SWAP_IO_SPACE @@ -336,6 +338,7 @@ config MIPS_MALTA select SYS_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_MULTITHREADING help This enables support for the MIPS Technologies Malta evaluation board. @@ -358,7 +361,7 @@ config MIPS_SEAD board. config WR_PPMC - bool "Support for Wind River PPMC board" + bool "Wind River PPMC board" select IRQ_CPU select BOOT_ELF32 select DMA_NONCOHERENT @@ -536,6 +539,7 @@ config PMC_YOSEMITE select SYS_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_HIGHMEM + select SYS_SUPPORTS_SMP help Yosemite is an evaluation board for the RM9000x2 processor manufactured by PMC-Sierra. @@ -590,6 +594,7 @@ config SGI_IP22 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN + select SYS_SUPPORTS_SMP help This are the SGI Indy, Challenge S and Indigo2, as well as certain OEM variants like the Tandem CMN B006S. To compile a Linux kernel @@ -601,6 +606,7 @@ config SGI_IP27 select ARC64 select BOOT_ELF64 select DMA_IP27 + select EARLY_PRINTK select HW_HAS_PCI select PCI_DOMAINS select SYS_HAS_CPU_R10000 @@ -1249,7 +1255,7 @@ config CPU_R6000 select CPU_SUPPORTS_32BIT_KERNEL help MIPS Technologies R6000 and R6000A series processors. Note these - processors are extremly rare and the support for them is incomplete. + processors are extremely rare and the support for them is incomplete. config CPU_NEVADA bool "RM52xx" @@ -1370,7 +1376,7 @@ config SYS_HAS_CPU_SB1 endmenu # -# These two indicate any levelof the MIPS32 and MIPS64 architecture +# These two indicate any level of the MIPS32 and MIPS64 architecture # config CPU_MIPS32 bool @@ -1381,7 +1387,7 @@ config CPU_MIPS64 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 # -# These two indicate the revision of the architecture, either 32 bot 64 bit. +# These two indicate the revision of the architecture, either Release 1 or Release 2 # config CPU_MIPSR1 bool @@ -1474,6 +1480,13 @@ config IP22_CPU_SCACHE bool select BOARD_SCACHE +# +# Support for a MIPS32 / MIPS64 style S-caches +# +config MIPS_CPU_SCACHE + bool + select BOARD_SCACHE + config R5000_CPU_SCACHE bool select BOARD_SCACHE @@ -1493,32 +1506,57 @@ config SIBYTE_DMA_PAGEOPS config CPU_HAS_PREFETCH bool -config MIPS_MT - bool "Enable MIPS MT" - choice prompt "MIPS MT options" - depends on MIPS_MT + +config MIPS_MT_DISABLED + bool "Disable multithreading support." + help + Use this option if your workload can't take advantage of + MIPS hardware multithreading support. On systems that don't have + the option of an MT-enabled processor this option will be the only + option in this menu. config MIPS_MT_SMTC bool "SMTC: Use all TCs on all VPEs for SMP" + depends on CPU_MIPS32_R2 + #depends on CPU_MIPS64_R2 # once there is hardware ... + depends on SYS_SUPPORTS_MULTITHREADING select CPU_MIPSR2_IRQ_VI select CPU_MIPSR2_SRS + select MIPS_MT select SMP + help + This is a kernel model which is known a SMTC or lately has been + marketesed into SMVP. config MIPS_MT_SMP bool "Use 1 TC on each available VPE for SMP" + depends on SYS_SUPPORTS_MULTITHREADING + select CPU_MIPSR2_IRQ_VI + select CPU_MIPSR2_SRS + select MIPS_MT select SMP + help + This is a kernel model which is also known a VSMP or lately + has been marketesed into SMVP. config MIPS_VPE_LOADER bool "VPE loader support." - depends on MIPS_MT + depends on SYS_SUPPORTS_MULTITHREADING + select MIPS_MT help Includes a loader for loading an elf relocatable object onto another VPE and running it. endchoice +config MIPS_MT + bool + +config SYS_SUPPORTS_MULTITHREADING + bool + config MIPS_MT_FPAFF bool "Dynamic FPU affinity for FP-intensive threads" depends on MIPS_MT @@ -1575,32 +1613,23 @@ config CPU_HAS_LLSC config CPU_HAS_WB bool +# +# Vectored interrupt mode is an R2 feature +# config CPU_MIPSR2_IRQ_VI - bool "Vectored interrupt mode" - depends on CPU_MIPSR2 - help - Vectored interrupt mode allowing faster dispatching of interrupts. - The board support code needs to be written to take advantage of this - mode. Compatibility code is included to allow the kernel to run on - a CPU that does not support vectored interrupts. It's safe to - say Y here. + bool +# +# Extended interrupt mode is an R2 feature +# config CPU_MIPSR2_IRQ_EI - bool "External interrupt controller mode" - depends on CPU_MIPSR2 - help - Extended interrupt mode takes advantage of an external interrupt - controller to allow fast dispatching from many possible interrupt - sources. Say N unless you know that external interrupt support is - required. + bool +# +# Shadow registers are an R2 feature +# config CPU_MIPSR2_SRS - bool "Make shadow set registers available for interrupt handlers" - depends on CPU_MIPSR2_IRQ_VI || CPU_MIPSR2_IRQ_EI - help - Allow the kernel to use shadow register sets for fast interrupts. - Interrupt handlers must be specially written to use shadow sets. - Say N unless you know that shadow register set upport is needed. + bool config CPU_HAS_SYNC bool @@ -1681,8 +1710,8 @@ source "mm/Kconfig" config SMP bool "Multi-Processing support" - depends on CPU_RM9000 || ((SIBYTE_BCM1x80 || SIBYTE_BCM1x55 || SIBYTE_SB1250 || QEMU) && !SIBYTE_STANDALONE) || SGI_IP27 || MIPS_MT_SMP || MIPS_MT_SMTC - ---help--- + depends on SYS_SUPPORTS_SMP + help This enables support for systems with more than one CPU. If you have a system with only one CPU, like most personal computers, say N. If you have a system with more than one CPU, say Y. @@ -1701,6 +1730,9 @@ config SMP If you don't know what to do here, say N. +config SYS_SUPPORTS_SMP + bool + config NR_CPUS int "Maximum number of CPUs (2-64)" range 2 64 diff --git a/arch/mips/Makefile b/arch/mips/Makefile index d593014..ebbb9ad 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -374,6 +374,7 @@ core-$(CONFIG_PMC_YOSEMITE) += arch/mips/pmc-sierra/yosemite/ cflags-$(CONFIG_PMC_YOSEMITE) += -Iinclude/asm-mips/mach-yosemite load-$(CONFIG_PMC_YOSEMITE) += 0xffffffff80100000 +# # Qemu simulating MIPS32 4Kc # core-$(CONFIG_QEMU) += arch/mips/qemu/ diff --git a/arch/mips/au1000/common/dbdma.c b/arch/mips/au1000/common/dbdma.c index 6ee090b..a547e47 100644 --- a/arch/mips/au1000/common/dbdma.c +++ b/arch/mips/au1000/common/dbdma.c @@ -290,7 +290,7 @@ au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, /* If kmalloc fails, it is caught below same * as a channel not available. */ - ctp = kmalloc(sizeof(chan_tab_t), GFP_KERNEL); + ctp = kmalloc(sizeof(chan_tab_t), GFP_ATOMIC); chan_tab_ptr[i] = ctp; break; } @@ -730,6 +730,8 @@ au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes) return rv; } +EXPORT_SYMBOL_GPL(au1xxx_dbdma_get_dest); + void au1xxx_dbdma_stop(u32 chanid) { @@ -821,6 +823,8 @@ au1xxx_get_dma_residue(u32 chanid) return rv; } +EXPORT_SYMBOL_GPL(au1xxx_get_dma_residue); + void au1xxx_dbdma_chan_free(u32 chanid) { diff --git a/arch/mips/au1000/common/irq.c b/arch/mips/au1000/common/irq.c index da74ac2..12d6ede 100644 --- a/arch/mips/au1000/common/irq.c +++ b/arch/mips/au1000/common/irq.c @@ -585,13 +585,13 @@ void intc1_req1_irqdispatch(struct pt_regs *regs) * au_sleep function in power.c.....maybe I should just pm_register() * them instead? */ -static uint sleep_intctl_config0[2]; -static uint sleep_intctl_config1[2]; -static uint sleep_intctl_config2[2]; -static uint sleep_intctl_src[2]; -static uint sleep_intctl_assign[2]; -static uint sleep_intctl_wake[2]; -static uint sleep_intctl_mask[2]; +static unsigned int sleep_intctl_config0[2]; +static unsigned int sleep_intctl_config1[2]; +static unsigned int sleep_intctl_config2[2]; +static unsigned int sleep_intctl_src[2]; +static unsigned int sleep_intctl_assign[2]; +static unsigned int sleep_intctl_wake[2]; +static unsigned int sleep_intctl_mask[2]; void save_au1xxx_intctl(void) diff --git a/arch/mips/au1000/common/power.c b/arch/mips/au1000/common/power.c index f492631..b035513 100644 --- a/arch/mips/au1000/common/power.c +++ b/arch/mips/au1000/common/power.c @@ -80,17 +80,17 @@ static DEFINE_SPINLOCK(pm_lock); * We only have to save/restore registers that aren't otherwise * done as part of a driver pm_* function. */ -static uint sleep_aux_pll_cntrl; -static uint sleep_cpu_pll_cntrl; -static uint sleep_pin_function; -static uint sleep_uart0_inten; -static uint sleep_uart0_fifoctl; -static uint sleep_uart0_linectl; -static uint sleep_uart0_clkdiv; -static uint sleep_uart0_enable; -static uint sleep_usbhost_enable; -static uint sleep_usbdev_enable; -static uint sleep_static_memctlr[4][3]; +static unsigned int sleep_aux_pll_cntrl; +static unsigned int sleep_cpu_pll_cntrl; +static unsigned int sleep_pin_function; +static unsigned int sleep_uart0_inten; +static unsigned int sleep_uart0_fifoctl; +static unsigned int sleep_uart0_linectl; +static unsigned int sleep_uart0_clkdiv; +static unsigned int sleep_uart0_enable; +static unsigned int sleep_usbhost_enable; +static unsigned int sleep_usbdev_enable; +static unsigned int sleep_static_memctlr[4][3]; /* Define this to cause the value you write to /proc/sys/pm/sleep to * set the TOY timer for the amount of time you want to sleep. diff --git a/arch/mips/au1000/csb250/init.c b/arch/mips/au1000/csb250/init.c index a4898b1..83f1b31 100644 --- a/arch/mips/au1000/csb250/init.c +++ b/arch/mips/au1000/csb250/init.c @@ -65,9 +65,9 @@ int __init prom_init(int argc, char **argv, char **envp, int *prom_vec) /* We use a0 and a1 to pass initrd start and size. */ - if (((uint) argc > 0) && ((uint)argv > 0)) { - my_initrd_start = (uint)argc; - my_initrd_size = (uint)argv; + if (((unsigned int) argc > 0) && ((uint)argv > 0)) { + my_initrd_start = (unsigned int)argc; + my_initrd_size = (unsigned int)argv; } /* First argv is ignored. diff --git a/arch/mips/basler/excite/excite_setup.c b/arch/mips/basler/excite/excite_setup.c index 005b025..3d7670e 100644 --- a/arch/mips/basler/excite/excite_setup.c +++ b/arch/mips/basler/excite/excite_setup.c @@ -254,7 +254,7 @@ static int __init excite_platform_init(void) return 0; } -void __init plat_setup(void) +void __init plat_mem_setup(void) { volatile u32 * const boot_ocd_base = (u32 *) 0xbf7fc000; diff --git a/arch/mips/ddb5xxx/common/prom.c b/arch/mips/ddb5xxx/common/prom.c index 00c62c1..20c845c 100644 --- a/arch/mips/ddb5xxx/common/prom.c +++ b/arch/mips/ddb5xxx/common/prom.c @@ -21,8 +21,6 @@ const char *get_system_type(void) { switch (mips_machtype) { - case MACH_NEC_DDB5074: return "NEC DDB Vrc-5074"; - case MACH_NEC_DDB5476: return "NEC DDB Vrc-5476"; case MACH_NEC_DDB5477: return "NEC DDB Vrc-5477"; case MACH_NEC_ROCKHOPPER: return "NEC Rockhopper"; case MACH_NEC_ROCKHOPPERII: return "NEC RockhopperII"; diff --git a/arch/mips/gt64120/common/Makefile b/arch/mips/gt64120/common/Makefile index eba5051..1ef676e 100644 --- a/arch/mips/gt64120/common/Makefile +++ b/arch/mips/gt64120/common/Makefile @@ -3,4 +3,3 @@ # obj-y += time.o -obj-$(CONFIG_PCI) += pci.o diff --git a/arch/mips/gt64120/common/pci.c b/arch/mips/gt64120/common/pci.c deleted file mode 100644 index e9e5419..0000000 --- a/arch/mips/gt64120/common/pci.c +++ /dev/null @@ -1,147 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * Galileo Evaluation Boards PCI support. - * - * The general-purpose functions to read/write and configure the GT64120A's - * PCI registers (function names start with pci0 or pci1) are either direct - * copies of functions written by Galileo Technology, or are modifications - * of their functions to work with Linux 2.4 vs Linux 2.2. These functions - * are Copyright - Galileo Technology. - * - * Other functions are derived from other MIPS PCI implementations, or were - * written by RidgeRun, Inc, Copyright (C) 2000 RidgeRun, Inc. - * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include <linux/init.h> -#include <linux/types.h> -#include <linux/pci.h> -#include <linux/kernel.h> -#include <asm/gt64120.h> - -#define SELF 0 - -/* - * pciXReadConfigReg - Read from a PCI configuration register - * - Make sure the GT is configured as a master before - * reading from another device on the PCI. - * - The function takes care of Big/Little endian conversion. - * INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI - * spec) - * pciDevNum: The device number needs to be addressed. - * RETURNS: data , if the data == 0xffffffff check the master abort bit in the - * cause register to make sure the data is valid - * - * Configuration Address 0xCF8: - * - * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number - * |congif|Reserved| Bus |Device|Function|Register|00| - * |Enable| |Number|Number| Number | Number | | <=field Name - * - */ -static unsigned int pci0ReadConfigReg(int offset, struct pci_dev *device) -{ - unsigned int DataForRegCf8; - unsigned int data; - - DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) | - (PCI_FUNC(device->devfn) << 8) | - (offset & ~0x3)) | 0x80000000; - GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8); - - /* - * The casual observer might wonder why the READ is duplicated here, - * rather than immediately following the WRITE, and just have the swap - * in the "if". That's because there is a latency problem with trying - * to read immediately after setting up the address register. The "if" - * check gives enough time for the address to stabilize, so the READ - * can work. - */ - if (PCI_SLOT(device->devfn) == SELF) /* This board */ - return GT_READ(GT_PCI0_CFGDATA_OFS); - else /* PCI is little endian so swap the Data. */ - return __GT_READ(GT_PCI0_CFGDATA_OFS); -} - -/* - * pciXWriteConfigReg - Write to a PCI configuration register - * - Make sure the GT is configured as a master before - * writingto another device on the PCI. - * - The function takes care of Big/Little endian conversion. - * Inputs: unsigned int regOffset: The register offset as it apears in the - * GT spec - * (or any other PCI device spec) - * pciDevNum: The device number needs to be addressed. - * - * Configuration Address 0xCF8: - * - * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number - * |congif|Reserved| Bus |Device|Function|Register|00| - * |Enable| |Number|Number| Number | Number | | <=field Name - * - */ -static void pci0WriteConfigReg(unsigned int offset, - struct pci_dev *device, unsigned int data) -{ - unsigned int DataForRegCf8; - - DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) | - (PCI_FUNC(device->devfn) << 8) | - (offset & ~0x3)) | 0x80000000; - GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8); - - if (PCI_SLOT(device->devfn) == SELF) /* This board */ - GT_WRITE(GT_PCI0_CFGDATA_OFS, data); - else /* configuration Transaction over the pci. */ - __GT_WRITE(GT_PCI0_CFGDATA_OFS, data); -} - -extern struct pci_ops gt64120_pci_ops; - -void __init pcibios_init(void) -{ - u32 tmp; - struct pci_dev controller; - - controller.devfn = SELF; - - tmp = GT_READ(GT_PCI0_CMD_OFS); /* Huh??? -- Ralf */ - tmp = GT_READ(GT_PCI0_BARE_OFS); - - /* - * You have to enable bus mastering to configure any other - * card on the bus. - */ - tmp = pci0ReadConfigReg(PCI_COMMAND, &controller); - tmp |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR; - pci0WriteConfigReg(PCI_COMMAND, &controller, tmp); - - /* - * Reset PCI I/O and PCI MEM values to ones supported by EVM. - */ - ioport_resource.start = GT_PCI_IO_BASE; - ioport_resource.end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1; - iomem_resource.start = GT_PCI_MEM_BASE; - iomem_resource.end = GT_PCI_MEM_BASE + GT_PCI_MEM_SIZE - 1; - - pci_scan_bus(0, >64120_pci_ops, NULL); -} diff --git a/arch/mips/gt64120/momenco_ocelot/setup.c b/arch/mips/gt64120/momenco_ocelot/setup.c index 1193a22..9804642 100644 --- a/arch/mips/gt64120/momenco_ocelot/setup.c +++ b/arch/mips/gt64120/momenco_ocelot/setup.c @@ -164,8 +164,8 @@ void __init plat_mem_setup(void) pm_power_off = momenco_ocelot_power_off; /* - * initrd_start = (ulong)ocelot_initrd_start; - * initrd_end = (ulong)ocelot_initrd_start + (ulong)ocelot_initrd_size; + * initrd_start = (unsigned long)ocelot_initrd_start; + * initrd_end = (unsigned long)ocelot_initrd_start + (ulong)ocelot_initrd_size; * initrd_below_start_ok = 1; */ diff --git a/arch/mips/gt64120/wrppmc/Makefile b/arch/mips/gt64120/wrppmc/Makefile index 72606b9..7cf5220 100644 --- a/arch/mips/gt64120/wrppmc/Makefile +++ b/arch/mips/gt64120/wrppmc/Makefile @@ -9,6 +9,6 @@ # Makefile for the Wind River MIPS 4KC PPMC Eval Board # -obj-y += int-handler.o irq.o reset.o setup.o time.o pci.o +obj-y += irq.o reset.o setup.o time.o pci.o EXTRA_AFLAGS := $(CFLAGS) diff --git a/arch/mips/gt64120/wrppmc/int-handler.S b/arch/mips/gt64120/wrppmc/int-handler.S deleted file mode 100644 index edee7b3..0000000 --- a/arch/mips/gt64120/wrppmc/int-handler.S +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1995, 1996, 1997, 2003 by Ralf Baechle - * Copyright (C) Wind River System Inc. Rongkai.Zhan <rongkai.zhan@windriver.com> - */ -#include <asm/asm.h> -#include <asm/mipsregs.h> -#include <asm/addrspace.h> -#include <asm/regdef.h> -#include <asm/stackframe.h> -#include <asm/mach-wrppmc/mach-gt64120.h> - - .align 5 - .set noat -NESTED(handle_IRQ, PT_SIZE, sp) - SAVE_ALL - CLI # Important: mark KERNEL mode ! - .set at - - mfc0 t0, CP0_CAUSE # get pending interrupts - mfc0 t1, CP0_STATUS # get enabled interrupts - and t0, t0, t1 # get allowed interrupts - andi t0, t0, 0xFF00 - beqz t0, 1f - move a1, sp # Prepare 'struct pt_regs *regs' pointer - - andi t1, t0, CAUSEF_IP7 # CPU Compare/Count internal timer - bnez t1, handle_cputimer_irq - andi t1, t0, CAUSEF_IP6 # UART 16550 port - bnez t1, handle_uart_irq - andi t1, t0, CAUSEF_IP3 # PCI INT_A - bnez t1, handle_pci_intA_irq - - /* wrong alarm or masked ... */ -1: j spurious_interrupt - nop -END(handle_IRQ) - - .align 5 -handle_cputimer_irq: - li a0, WRPPMC_MIPS_TIMER_IRQ - jal do_IRQ - j ret_from_irq - - .align 5 -handle_uart_irq: - li a0, WRPPMC_UART16550_IRQ - jal do_IRQ - j ret_from_irq - - .align 5 -handle_pci_intA_irq: - li a0, WRPPMC_PCI_INTA_IRQ - jal do_IRQ - j ret_from_irq - diff --git a/arch/mips/gt64120/wrppmc/irq.c b/arch/mips/gt64120/wrppmc/irq.c index 8605687..8d75a43 100644 --- a/arch/mips/gt64120/wrppmc/irq.c +++ b/arch/mips/gt64120/wrppmc/irq.c @@ -30,7 +30,19 @@ #include <asm/irq_cpu.h> #include <asm/gt64120.h> -extern asmlinkage void handle_IRQ(void); +asmlinkage void plat_irq_dispatch(struct pt_regs *regs) +{ + unsigned int pending = read_c0_status() & read_c0_cause(); + + if (pending & STATUSF_IP7) + do_IRQ(WRPPMC_MIPS_TIMER_IRQ, regs); /* CPU Compare/Count internal timer */ + else if (pending & STATUSF_IP6) + do_IRQ(WRPPMC_UART16550_IRQ, regs); /* UART 16550 port */ + else if (pending & STATUSF_IP3) + do_IRQ(WRPPMC_PCI_INTA_IRQ, regs); /* PCI INT_A */ + else + spurious_interrupt(regs); +} /** * Initialize GT64120 Interrupt Controller @@ -50,12 +62,6 @@ void gt64120_init_pic(void) void __init arch_init_irq(void) { - /* enable all CPU interrupt bits. */ - set_c0_status(ST0_IM); /* IE bit is still 0 */ - - /* Install MIPS Interrupt Trap Vector */ - set_except_vector(0, handle_IRQ); - /* IRQ 0 - 7 are for MIPS common irq_cpu controller */ mips_cpu_irq_init(0); diff --git a/arch/mips/gt64120/wrppmc/setup.c b/arch/mips/gt64120/wrppmc/setup.c index 20c591e..2db6375 100644 --- a/arch/mips/gt64120/wrppmc/setup.c +++ b/arch/mips/gt64120/wrppmc/setup.c @@ -125,7 +125,7 @@ static void wrppmc_setup_serial(void) } #endif -void __init plat_setup(void) +void __init plat_mem_setup(void) { extern void wrppmc_time_init(void); extern void wrppmc_timer_setup(struct irqaction *); diff --git a/arch/mips/gt64120/wrppmc/time.c b/arch/mips/gt64120/wrppmc/time.c index 175d22a..6c24a82 100644 --- a/arch/mips/gt64120/wrppmc/time.c +++ b/arch/mips/gt64120/wrppmc/time.c @@ -31,10 +31,6 @@ void __init wrppmc_timer_setup(struct irqaction *irq) { /* Install ISR for timer interrupt */ setup_irq(WRPPMC_MIPS_TIMER_IRQ, irq); - - /* to generate the first timer interrupt */ - write_c0_compare(mips_hpt_frequency/HZ); - write_c0_count(0); } /* diff --git a/arch/mips/kernel/apm.c b/arch/mips/kernel/apm.c index 15f46b4..7bdbcd8 100644 --- a/arch/mips/kernel/apm.c +++ b/arch/mips/kernel/apm.c @@ -260,7 +260,7 @@ static unsigned int apm_poll(struct file *fp, poll_table * wait) * has acknowledge does the actual suspend happen. */ static int -apm_ioctl(struct inode * inode, struct file *filp, u_int cmd, u_long arg) +apm_ioctl(struct inode * inode, struct file *filp, unsigned int cmd, unsigned long arg) { struct apm_user *as = filp->private_data; unsigned long flags; diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 8c2c359..e045aba 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -597,8 +597,6 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c) break; case PRID_IMP_25KF: c->cputype = CPU_25KF; - /* Probe for L2 cache */ - c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; break; case PRID_IMP_34K: c->cputype = CPU_34K; diff --git a/arch/mips/kernel/entry.S b/arch/mips/kernel/entry.S index a9c6de1..4575651 100644 --- a/arch/mips/kernel/entry.S +++ b/arch/mips/kernel/entry.S @@ -87,7 +87,7 @@ FEXPORT(restore_all) # restore full frame ori v1, v0, TCSTATUS_IXMT mtc0 v1, CP0_TCSTATUS andi v0, TCSTATUS_IXMT - ehb + _ehb mfc0 t0, CP0_TCCONTEXT DMT 9 # dmt t1 jal mips_ihb @@ -95,7 +95,7 @@ FEXPORT(restore_all) # restore full frame andi t3, t0, 0xff00 or t2, t2, t3 mtc0 t2, CP0_STATUS - ehb + _ehb andi t1, t1, VPECONTROL_TE beqz t1, 1f EMT @@ -105,7 +105,7 @@ FEXPORT(restore_all) # restore full frame xori v1, v1, TCSTATUS_IXMT or v1, v0, v1 mtc0 v1, CP0_TCSTATUS - ehb + _ehb xor t0, t0, t3 mtc0 t0, CP0_TCCONTEXT #endif /* CONFIG_MIPS_MT_SMTC */ diff --git a/arch/mips/kernel/gdb-low.S b/arch/mips/kernel/gdb-low.S index 5fd7a8a..8760131 100644 --- a/arch/mips/kernel/gdb-low.S +++ b/arch/mips/kernel/gdb-low.S @@ -291,7 +291,7 @@ ori t1, t2, TCSTATUS_IXMT mtc0 t1, CP0_TCSTATUS andi t2, t2, TCSTATUS_IXMT - ehb + _ehb DMT 9 # dmt t1 jal mips_ihb nop @@ -310,7 +310,7 @@ xori t1, t1, TCSTATUS_IXMT or t1, t1, t2 mtc0 t1, CP0_TCSTATUS - ehb + _ehb #endif /* CONFIG_MIPS_MT_SMTC */ LONG_L v0, GDB_FR_STATUS(sp) LONG_L v1, GDB_FR_EPC(sp) diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index ff7af36..6888cde 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -214,7 +214,7 @@ NESTED(except_vec_vi_handler, 0, sp) mtc0 t0, CP0_TCCONTEXT xor t1, t1, t0 mtc0 t1, CP0_STATUS - ehb + _ehb #endif /* CONFIG_MIPS_MT_SMTC */ CLI move a0, sp diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S index bdf6f6e..c018098 100644 --- a/arch/mips/kernel/head.S +++ b/arch/mips/kernel/head.S @@ -96,7 +96,7 @@ /* Clear TKSU, leave IXMT */ xori t0, 0x00001800 mtc0 t0, CP0_TCSTATUS - ehb + _ehb /* We need to leave the global IE bit set, but clear EXL...*/ mfc0 t0, CP0_STATUS or t0, ST0_CU0 | ST0_EXL | ST0_ERL | \set | \clr diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S index db94e55..e1b85e6 100644 --- a/arch/mips/kernel/r4k_switch.S +++ b/arch/mips/kernel/r4k_switch.S @@ -94,7 +94,7 @@ ori t1, t2, TCSTATUS_IXMT mtc0 t1, CP0_TCSTATUS andi t2, t2, TCSTATUS_IXMT - ehb + _ehb DMT 8 # dmt t0 move t1,ra jal mips_ihb @@ -109,7 +109,7 @@ or a2, t1 mtc0 a2, CP0_STATUS #ifdef CONFIG_MIPS_MT_SMTC - ehb + _ehb andi t0, t0, VPECONTROL_TE beqz t0, 1f emt @@ -118,7 +118,7 @@ xori t1, t1, TCSTATUS_IXMT or t1, t1, t2 mtc0 t1, CP0_TCSTATUS - ehb + _ehb #endif /* CONFIG_MIPS_MT_SMTC */ move v0, a0 jr ra diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S index 2d2fdf7..6344be4 100644 --- a/arch/mips/kernel/scall32-o32.S +++ b/arch/mips/kernel/scall32-o32.S @@ -647,6 +647,7 @@ einval: li v0, -EINVAL sys sys_unshare 1 sys sys_splice 4 sys sys_sync_file_range 7 /* 4305 */ + sys sys_tee 4 .endm /* We pre-compute the number of _instruction_ bytes needed to diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S index 9ba7508..12d96c7 100644 --- a/arch/mips/kernel/scall64-64.S +++ b/arch/mips/kernel/scall64-64.S @@ -462,3 +462,4 @@ sys_call_table: PTR sys_unshare PTR sys_splice PTR sys_sync_file_range + PTR sys_tee /* 5265 */ diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S index 942aca2..6856985 100644 --- a/arch/mips/kernel/scall64-n32.S +++ b/arch/mips/kernel/scall64-n32.S @@ -388,3 +388,4 @@ EXPORT(sysn32_call_table) PTR sys_unshare PTR sys_splice PTR sys_sync_file_range + PTR sys_tee diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S index 8efb23a..0e63293 100644 --- a/arch/mips/kernel/scall64-o32.S +++ b/arch/mips/kernel/scall64-o32.S @@ -510,4 +510,5 @@ sys_call_table: PTR sys_unshare PTR sys_splice PTR sys32_sync_file_range /* 4305 */ + PTR sys_tee .size sys_call_table,.-sys_call_table diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index bfcec8d..d3e0871 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -488,6 +488,9 @@ static inline void resource_init(void) { int i; + if (UNCAC_BASE != IO_BASE) + return; + code_resource.start = virt_to_phys(&_text); code_resource.end = virt_to_phys(&_etext) - 1; data_resource.start = virt_to_phys(&_etext); diff --git a/arch/mips/kernel/smtc-asm.S b/arch/mips/kernel/smtc-asm.S index c9d6519..72c6d98 100644 --- a/arch/mips/kernel/smtc-asm.S +++ b/arch/mips/kernel/smtc-asm.S @@ -52,12 +52,12 @@ FEXPORT(__smtc_ipi_vector) .set noat /* Disable thread scheduling to make Status update atomic */ DMT 27 # dmt k1 - ehb + _ehb /* Set EXL */ mfc0 k0,CP0_STATUS ori k0,k0,ST0_EXL mtc0 k0,CP0_STATUS - ehb + _ehb /* Thread scheduling now inhibited by EXL. Restore TE state. */ andi k1,k1,VPECONTROL_TE beqz k1,1f @@ -82,7 +82,7 @@ FEXPORT(__smtc_ipi_vector) li k1,ST0_CU0 or k1,k1,k0 mtc0 k1,CP0_STATUS - ehb + _ehb get_saved_sp /* Interrupting TC will have pre-set values in slots in the new frame */ 2: subu k1,k1,PT_SIZE @@ -90,7 +90,7 @@ FEXPORT(__smtc_ipi_vector) lw k0,PT_TCSTATUS(k1) /* Write it to TCStatus to restore CU/KSU/IXMT state */ mtc0 k0,$2,1 - ehb + _ehb lw k0,PT_EPC(k1) mtc0 k0,CP0_EPC /* Save all will redundantly recompute the SP, but use it for now */ @@ -116,7 +116,7 @@ LEAF(self_ipi) mfc0 t0,CP0_TCSTATUS ori t1,t0,TCSTATUS_IXMT mtc0 t1,CP0_TCSTATUS - ehb + _ehb /* We know we're in kernel mode, so prepare stack frame */ subu t1,sp,PT_SIZE sw ra,PT_EPC(t1) diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c index 5e8a18a..6da8c68 100644 --- a/arch/mips/kernel/syscall.c +++ b/arch/mips/kernel/syscall.c @@ -301,7 +301,7 @@ asmlinkage int _sys_sysmips(int cmd, long arg1, int arg2, int arg3) * * This is really horribly ugly. */ -asmlinkage int sys_ipc (uint call, int first, int second, +asmlinkage int sys_ipc (unsigned int call, int first, int second, unsigned long third, void __user *ptr, long fifth) { int version, ret; @@ -359,18 +359,18 @@ asmlinkage int sys_ipc (uint call, int first, int second, case SHMAT: switch (version) { default: { - ulong raddr; + unsigned long raddr; ret = do_shmat (first, (char __user *) ptr, second, &raddr); if (ret) return ret; - return put_user (raddr, (ulong __user *) third); + return put_user (raddr, (unsigned long __user *) third); } case 1: /* iBCS2 emulator entry point */ if (!segment_eq(get_fs(), get_ds())) return -EINVAL; return do_shmat (first, (char __user *) ptr, second, - (ulong *) third); + (unsigned long *) third); } case SHMDT: return sys_shmdt ((char __user *)ptr); diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index ad16ece..6797193 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1050,7 +1050,7 @@ void *set_except_vector(int n, void *addr) return (void *)old_handler; } -#ifdef CONFIG_CPU_MIPSR2 +#ifdef CONFIG_CPU_MIPSR2_SRS /* * MIPSR2 shadow register set allocation * FIXME: SMP... @@ -1069,11 +1069,9 @@ static struct shadow_registers { static void mips_srs_init(void) { -#ifdef CONFIG_CPU_MIPSR2_SRS shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1; printk(KERN_INFO "%d MIPSR2 register sets available\n", shadow_registers.sr_supported); -#endif shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */ } @@ -1198,7 +1196,14 @@ void *set_vi_handler(int n, void *addr) { return set_vi_srs_handler(n, addr, 0); } -#endif + +#else + +static inline void mips_srs_init(void) +{ +} + +#endif /* CONFIG_CPU_MIPSR2_SRS */ /* * This is used by native signal handling @@ -1388,9 +1393,7 @@ void __init trap_init(void) else ebase = CAC_BASE; -#ifdef CONFIG_CPU_MIPSR2 mips_srs_init(); -#endif per_cpu_trap_init(); diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile index 4a622011..19e41fd 100644 --- a/arch/mips/mm/Makefile +++ b/arch/mips/mm/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_CPU_VR41XX) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o obj-$(CONFIG_RM7000_CPU_SCACHE) += sc-rm7k.o +obj-$(CONFIG_MIPS_CPU_SCACHE) += sc-mips.o # # Choose one DMA coherency model diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 4a43924..75d887e 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -60,13 +60,13 @@ static unsigned long scache_size __read_mostly; /* * Dummy cache handling routines for machines without boardcaches */ -static void no_sc_noop(void) {} +static void cache_noop(void) {} static struct bcache_ops no_sc_ops = { - .bc_enable = (void *)no_sc_noop, - .bc_disable = (void *)no_sc_noop, - .bc_wback_inv = (void *)no_sc_noop, - .bc_inv = (void *)no_sc_noop + .bc_enable = (void *)cache_noop, + .bc_disable = (void *)cache_noop, + .bc_wback_inv = (void *)cache_noop, + .bc_inv = (void *)cache_noop }; struct bcache_ops *bcops = &no_sc_ops; @@ -94,7 +94,9 @@ static inline void r4k_blast_dcache_page_setup(void) { unsigned long dc_lsize = cpu_dcache_line_size(); - if (dc_lsize == 16) + if (dc_lsize == 0) + r4k_blast_dcache_page = (void *)cache_noop; + else if (dc_lsize == 16) r4k_blast_dcache_page = blast_dcache16_page; else if (dc_lsize == 32) r4k_blast_dcache_page = r4k_blast_dcache_page_dc32; @@ -106,7 +108,9 @@ static inline void r4k_blast_dcache_page_indexed_setup(void) { unsigned long dc_lsize = cpu_dcache_line_size(); - if (dc_lsize == 16) + if (dc_lsize == 0) + r4k_blast_dcache_page_indexed = (void *)cache_noop; + else if (dc_lsize == 16) r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed; else if (dc_lsize == 32) r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed; @@ -118,7 +122,9 @@ static inline void r4k_blast_dcache_setup(void) { unsigned long dc_lsize = cpu_dcache_line_size(); - if (dc_lsize == 16) + if (dc_lsize == 0) + r4k_blast_dcache = (void *)cache_noop; + else if (dc_lsize == 16) r4k_blast_dcache = blast_dcache16; else if (dc_lsize == 32) r4k_blast_dcache = blast_dcache32; @@ -201,7 +207,9 @@ static inline void r4k_blast_icache_page_setup(void) { unsigned long ic_lsize = cpu_icache_line_size(); - if (ic_lsize == 16) + if (ic_lsize == 0) + r4k_blast_icache_page = (void *)cache_noop; + else if (ic_lsize == 16) r4k_blast_icache_page = blast_icache16_page; else if (ic_lsize == 32) r4k_blast_icache_page = blast_icache32_page; @@ -216,7 +224,9 @@ static inline void r4k_blast_icache_page_indexed_setup(void) { unsigned long ic_lsize = cpu_icache_line_size(); - if (ic_lsize == 16) + if (ic_lsize == 0) + r4k_blast_icache_page_indexed = (void *)cache_noop; + else if (ic_lsize == 16) r4k_blast_icache_page_indexed = blast_icache16_page_indexed; else if (ic_lsize == 32) { if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) @@ -238,7 +248,9 @@ static inline void r4k_blast_icache_setup(void) { unsigned long ic_lsize = cpu_icache_line_size(); - if (ic_lsize == 16) + if (ic_lsize == 0) + r4k_blast_icache = (void *)cache_noop; + else if (ic_lsize == 16) r4k_blast_icache = blast_icache16; else if (ic_lsize == 32) { if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x()) @@ -258,7 +270,7 @@ static inline void r4k_blast_scache_page_setup(void) unsigned long sc_lsize = cpu_scache_line_size(); if (scache_size == 0) - r4k_blast_scache_page = (void *)no_sc_noop; + r4k_blast_scache_page = (void *)cache_noop; else if (sc_lsize == 16) r4k_blast_scache_page = blast_scache16_page; else if (sc_lsize == 32) @@ -276,7 +288,7 @@ static inline void r4k_blast_scache_page_indexed_setup(void) unsigned long sc_lsize = cpu_scache_line_size(); if (scache_size == 0) - r4k_blast_scache_page_indexed = (void *)no_sc_noop; + r4k_blast_scache_page_indexed = (void *)cache_noop; else if (sc_lsize == 16) r4k_blast_scache_page_indexed = blast_scache16_page_indexed; else if (sc_lsize == 32) @@ -294,7 +306,7 @@ static inline void r4k_blast_scache_setup(void) unsigned long sc_lsize = cpu_scache_line_size(); if (scache_size == 0) - r4k_blast_scache = (void *)no_sc_noop; + r4k_blast_scache = (void *)cache_noop; else if (sc_lsize == 16) r4k_blast_scache = blast_scache16; else if (sc_lsize == 32) @@ -508,7 +520,7 @@ static inline void local_r4k_flush_icache_range(void *args) unsigned long end = fir_args->end; if (!cpu_has_ic_fills_f_dc) { - if (end - start > dcache_size) { + if (end - start >= dcache_size) { r4k_blast_dcache(); } else { R4600_HIT_CACHEOP_WAR_IMPL; @@ -683,10 +695,12 @@ static void local_r4k_flush_cache_sigtramp(void * arg) unsigned long addr = (unsigned long) arg; R4600_HIT_CACHEOP_WAR_IMPL; - protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); + if (dc_lsize) + protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); if (!cpu_icache_snoops_remote_store && scache_size) protected_writeback_scache_line(addr & ~(sc_lsize - 1)); - protected_flush_icache_line(addr & ~(ic_lsize - 1)); + if (ic_lsize) + protected_flush_icache_line(addr & ~(ic_lsize - 1)); if (MIPS4K_ICACHE_REFILL_WAR) { __asm__ __volatile__ ( ".set push\n\t" @@ -973,8 +987,10 @@ static void __init probe_pcache(void) c->icache.waysize = icache_size / c->icache.ways; c->dcache.waysize = dcache_size / c->dcache.ways; - c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways); - c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways); + c->icache.sets = c->icache.linesz ? + icache_size / (c->icache.linesz * c->icache.ways) : 0; + c->dcache.sets = c->dcache.linesz ? + dcache_size / (c->dcache.linesz * c->dcache.ways) : 0; /* * R10000 and R12000 P-caches are odd in a positive way. They're 32kB @@ -993,10 +1009,16 @@ static void __init probe_pcache(void) break; case CPU_24K: case CPU_34K: - if (!(read_c0_config7() & (1 << 16))) + case CPU_74K: + if ((read_c0_config7() & (1 << 16))) { + /* effectively physically indexed dcache, + thus no virtual aliases. */ + c->dcache.flags |= MIPS_CACHE_PINDEX; + break; + } default: - if (c->dcache.waysize > PAGE_SIZE) - c->dcache.flags |= MIPS_CACHE_ALIASES; + if (c->dcache.waysize > PAGE_SIZE) + c->dcache.flags |= MIPS_CACHE_ALIASES; } switch (c->cputype) { @@ -1092,6 +1114,7 @@ static int __init probe_scache(void) extern int r5k_sc_init(void); extern int rm7k_sc_init(void); +extern int mips_sc_init(void); static void __init setup_scache(void) { @@ -1139,17 +1162,29 @@ static void __init setup_scache(void) return; default: + if (c->isa_level == MIPS_CPU_ISA_M32R1 || + c->isa_level == MIPS_CPU_ISA_M32R2 || + c->isa_level == MIPS_CPU_ISA_M64R1 || + c->isa_level == MIPS_CPU_ISA_M64R2) { +#ifdef CONFIG_MIPS_CPU_SCACHE + if (mips_sc_init ()) { + scache_size = c->scache.ways * c->scache.sets * c->scache.linesz; + printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n", + scache_size >> 10, + way_string[c->scache.ways], c->scache.linesz); + } +#else + if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT)) + panic("Dunno how to handle MIPS32 / MIPS64 second level cache"); +#endif + return; + } sc_present = 0; } if (!sc_present) return; - if ((c->isa_level == MIPS_CPU_ISA_M32R1 || - c->isa_level == MIPS_CPU_ISA_M64R1) && - !(c->scache.flags & MIPS_CACHE_NOT_PRESENT)) - panic("Dunno how to handle MIPS32 / MIPS64 second level cache"); - /* compute a couple of other cache variables */ c->scache.waysize = scache_size / c->scache.ways; @@ -1246,10 +1281,12 @@ void __init r4k_cache_init(void) * This code supports virtually indexed processors and will be * unnecessarily inefficient on physically indexed processors. */ - shm_align_mask = max_t( unsigned long, - c->dcache.sets * c->dcache.linesz - 1, - PAGE_SIZE - 1); - + if (c->dcache.linesz) + shm_align_mask = max_t( unsigned long, + c->dcache.sets * c->dcache.linesz - 1, + PAGE_SIZE - 1); + else + shm_align_mask = PAGE_SIZE-1; flush_cache_all = r4k_flush_cache_all; __flush_cache_all = r4k___flush_cache_all; flush_cache_mm = r4k_flush_cache_mm; diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c new file mode 100644 index 0000000..42b5096 --- /dev/null +++ b/arch/mips/mm/sc-mips.c @@ -0,0 +1,112 @@ +/* + * Copyright (C) 2006 Chris Dearman (chris@mips.com), + */ +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/sched.h> +#include <linux/mm.h> + +#include <asm/mipsregs.h> +#include <asm/bcache.h> +#include <asm/cacheops.h> +#include <asm/page.h> +#include <asm/pgtable.h> +#include <asm/system.h> +#include <asm/mmu_context.h> +#include <asm/r4kcache.h> + +/* + * MIPS32/MIPS64 L2 cache handling + */ + +/* + * Writeback and invalidate the secondary cache before DMA. + */ +static void mips_sc_wback_inv(unsigned long addr, unsigned long size) +{ + blast_scache_range(addr, addr + size); +} + +/* + * Invalidate the secondary cache before DMA. + */ +static void mips_sc_inv(unsigned long addr, unsigned long size) +{ + blast_inv_scache_range(addr, addr + size); +} + +static void mips_sc_enable(void) +{ + /* L2 cache is permanently enabled */ +} + +static void mips_sc_disable(void) +{ + /* L2 cache is permanently enabled */ +} + +static struct bcache_ops mips_sc_ops = { + .bc_enable = mips_sc_enable, + .bc_disable = mips_sc_disable, + .bc_wback_inv = mips_sc_wback_inv, + .bc_inv = mips_sc_inv +}; + +static inline int __init mips_sc_probe(void) +{ + struct cpuinfo_mips *c = ¤t_cpu_data; + unsigned int config1, config2; + unsigned int tmp; + + /* Mark as not present until probe completed */ + c->scache.flags |= MIPS_CACHE_NOT_PRESENT; + + /* Ignore anything but MIPSxx processors */ + if (c->isa_level != MIPS_CPU_ISA_M32R1 && + c->isa_level != MIPS_CPU_ISA_M32R2 && + c->isa_level != MIPS_CPU_ISA_M64R1 && + c->isa_level != MIPS_CPU_ISA_M64R2) + return 0; + + /* Does this MIPS32/MIPS64 CPU have a config2 register? */ + config1 = read_c0_config1(); + if (!(config1 & MIPS_CONF_M)) + return 0; + + config2 = read_c0_config2(); + tmp = (config2 >> 4) & 0x0f; + if (0 < tmp && tmp <= 7) + c->scache.linesz = 2 << tmp; + else + return 0; + + tmp = (config2 >> 8) & 0x0f; + if (0 <= tmp && tmp <= 7) + c->scache.sets = 64 << tmp; + else + return 0; + + tmp = (config2 >> 0) & 0x0f; + if (0 <= tmp && tmp <= 7) + c->scache.ways = tmp + 1; + else + return 0; + + c->scache.waysize = c->scache.sets * c->scache.linesz; + c->scache.waybit = __ffs(c->scache.waysize); + + c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; + + return 1; +} + +int __init mips_sc_init(void) +{ + int found = mips_sc_probe (); + if (found) { + mips_sc_enable(); + bcops = &mips_sc_ops; + } + return found; +} + diff --git a/arch/mips/momentum/jaguar_atx/setup.c b/arch/mips/momentum/jaguar_atx/setup.c index df14855..d041948 100644 --- a/arch/mips/momentum/jaguar_atx/setup.c +++ b/arch/mips/momentum/jaguar_atx/setup.c @@ -370,8 +370,8 @@ void __init plat_mem_setup(void) pm_power_off = momenco_jaguar_power_off; /* - * initrd_start = (ulong)jaguar_initrd_start; - * initrd_end = (ulong)jaguar_initrd_start + (ulong)jaguar_initrd_size; + * initrd_start = (unsigned long)jaguar_initrd_start; + * initrd_end = (unsigned long)jaguar_initrd_start + (ulong)jaguar_initrd_size; * initrd_below_start_ok = 1; */ diff --git a/arch/mips/momentum/ocelot_c/setup.c b/arch/mips/momentum/ocelot_c/setup.c index 257e1d1..a0ee006 100644 --- a/arch/mips/momentum/ocelot_c/setup.c +++ b/arch/mips/momentum/ocelot_c/setup.c @@ -242,8 +242,8 @@ void __init plat_mem_setup(void) pm_power_off = momenco_ocelot_power_off; /* - * initrd_start = (ulong)ocelot_initrd_start; - * initrd_end = (ulong)ocelot_initrd_start + (ulong)ocelot_initrd_size; + * initrd_start = (unsigned long)ocelot_initrd_start; + * initrd_end = (unsigned long)ocelot_initrd_start + (ulong)ocelot_initrd_size; * initrd_below_start_ok = 1; */ diff --git a/arch/mips/momentum/ocelot_g/setup.c b/arch/mips/momentum/ocelot_g/setup.c index 72143ab..39da02b 100644 --- a/arch/mips/momentum/ocelot_g/setup.c +++ b/arch/mips/momentum/ocelot_g/setup.c @@ -174,8 +174,8 @@ void __init plat_mem_setup(void) pm_power_off = momenco_ocelot_power_off; /* - * initrd_start = (ulong)ocelot_initrd_start; - * initrd_end = (ulong)ocelot_initrd_start + (ulong)ocelot_initrd_size; + * initrd_start = (unsigned long)ocelot_initrd_start; + * initrd_end = (unsigned long)ocelot_initrd_start + (ulong)ocelot_initrd_size; * initrd_below_start_ok = 1; */ diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c index f26a00e..a09c5f9 100644 --- a/arch/mips/oprofile/op_model_mipsxx.c +++ b/arch/mips/oprofile/op_model_mipsxx.c @@ -12,16 +12,70 @@ #include "op_impl.h" -#define M_PERFCTL_EXL (1UL << 0) -#define M_PERFCTL_KERNEL (1UL << 1) -#define M_PERFCTL_SUPERVISOR (1UL << 2) -#define M_PERFCTL_USER (1UL << 3) -#define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4) -#define M_PERFCTL_EVENT(event) ((event) << 5) -#define M_PERFCTL_WIDE (1UL << 30) -#define M_PERFCTL_MORE (1UL << 31) +#define M_PERFCTL_EXL (1UL << 0) +#define M_PERFCTL_KERNEL (1UL << 1) +#define M_PERFCTL_SUPERVISOR (1UL << 2) +#define M_PERFCTL_USER (1UL << 3) +#define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4) +#define M_PERFCTL_EVENT(event) ((event) << 5) +#define M_PERFCTL_VPEID(vpe) ((vpe) << 16) +#define M_PERFCTL_MT_EN(filter) ((filter) << 20) +#define M_TC_EN_ALL M_PERFCTL_MT_EN(0) +#define M_TC_EN_VPE M_PERFCTL_MT_EN(1) +#define M_TC_EN_TC M_PERFCTL_MT_EN(2) +#define M_PERFCTL_TCID(tcid) ((tcid) << 22) +#define M_PERFCTL_WIDE (1UL << 30) +#define M_PERFCTL_MORE (1UL << 31) + +#define M_COUNTER_OVERFLOW (1UL << 31) + +#ifdef CONFIG_MIPS_MT_SMP +#define WHAT (M_TC_EN_VPE | M_PERFCTL_VPEID(smp_processor_id())) +#else +#define WHAT 0 +#endif -#define M_COUNTER_OVERFLOW (1UL << 31) +#define __define_perf_accessors(r, n, np) \ + \ +static inline unsigned int r_c0_ ## r ## n(void) \ +{ \ + unsigned int cpu = smp_processor_id(); \ + \ + switch (cpu) { \ + case 0: \ + return read_c0_ ## r ## n(); \ + case 1: \ + return read_c0_ ## r ## np(); \ + default: \ + BUG(); \ + } \ +} \ + \ +static inline void w_c0_ ## r ## n(unsigned int value) \ +{ \ + unsigned int cpu = smp_processor_id(); \ + \ + switch (cpu) { \ + case 0: \ + write_c0_ ## r ## n(value); \ + return; \ + case 1: \ + write_c0_ ## r ## np(value); \ + return; \ + default: \ + BUG(); \ + } \ +} \ + +__define_perf_accessors(perfcntr, 0, 2) +__define_perf_accessors(perfcntr, 1, 3) +__define_perf_accessors(perfcntr, 2, 2) +__define_perf_accessors(perfcntr, 3, 2) + +__define_perf_accessors(perfctrl, 0, 2) +__define_perf_accessors(perfctrl, 1, 3) +__define_perf_accessors(perfctrl, 2, 2) +__define_perf_accessors(perfctrl, 3, 2) struct op_mips_model op_model_mipsxx_ops; @@ -66,17 +120,17 @@ static void mipsxx_cpu_setup (void *args) switch (counters) { case 4: - write_c0_perfctrl3(0); - write_c0_perfcntr3(reg.counter[3]); + w_c0_perfctrl3(0); + w_c0_perfcntr3(reg.counter[3]); case 3: - write_c0_perfctrl2(0); - write_c0_perfcntr2(reg.counter[2]); + w_c0_perfctrl2(0); + w_c0_perfcntr2(reg.counter[2]); case 2: - write_c0_perfctrl1(0); - write_c0_perfcntr1(reg.counter[1]); + w_c0_perfctrl1(0); + w_c0_perfcntr1(reg.counter[1]); case 1: - write_c0_perfctrl0(0); - write_c0_perfcntr0(reg.counter[0]); + w_c0_perfctrl0(0); + w_c0_perfcntr0(reg.counter[0]); } } @@ -87,13 +141,13 @@ static void mipsxx_cpu_start(void *args) switch (counters) { case 4: - write_c0_perfctrl3(reg.control[3]); + w_c0_perfctrl3(WHAT | reg.control[3]); case 3: - write_c0_perfctrl2(reg.control[2]); + w_c0_perfctrl2(WHAT | reg.control[2]); case 2: - write_c0_perfctrl1(reg.control[1]); + w_c0_perfctrl1(WHAT | reg.control[1]); case 1: - write_c0_perfctrl0(reg.control[0]); + w_c0_perfctrl0(WHAT | reg.control[0]); } } @@ -104,13 +158,13 @@ static void mipsxx_cpu_stop(void *args) switch (counters) { case 4: - write_c0_perfctrl3(0); + w_c0_perfctrl3(0); case 3: - write_c0_perfctrl2(0); + w_c0_perfctrl2(0); case 2: - write_c0_perfctrl1(0); + w_c0_perfctrl1(0); case 1: - write_c0_perfctrl0(0); + w_c0_perfctrl0(0); } } @@ -124,12 +178,12 @@ static int mipsxx_perfcount_handler(struct pt_regs *regs) switch (counters) { #define HANDLE_COUNTER(n) \ case n + 1: \ - control = read_c0_perfctrl ## n(); \ - counter = read_c0_perfcntr ## n(); \ + control = r_c0_perfctrl ## n(); \ + counter = r_c0_perfcntr ## n(); \ if ((control & M_PERFCTL_INTERRUPT_ENABLE) && \ (counter & M_COUNTER_OVERFLOW)) { \ oprofile_add_sample(regs, n); \ - write_c0_perfcntr ## n(reg.counter[n]); \ + w_c0_perfcntr ## n(reg.counter[n]); \ handled = 1; \ } HANDLE_COUNTER(3) @@ -143,35 +197,47 @@ static int mipsxx_perfcount_handler(struct pt_regs *regs) #define M_CONFIG1_PC (1 << 4) -static inline int n_counters(void) +static inline int __n_counters(void) { if (!(read_c0_config1() & M_CONFIG1_PC)) return 0; - if (!(read_c0_perfctrl0() & M_PERFCTL_MORE)) + if (!(r_c0_perfctrl0() & M_PERFCTL_MORE)) return 1; - if (!(read_c0_perfctrl1() & M_PERFCTL_MORE)) + if (!(r_c0_perfctrl1() & M_PERFCTL_MORE)) return 2; - if (!(read_c0_perfctrl2() & M_PERFCTL_MORE)) + if (!(r_c0_perfctrl2() & M_PERFCTL_MORE)) return 3; return 4; } +static inline int n_counters(void) +{ + int counters = __n_counters(); + +#ifndef CONFIG_SMP + if (current_cpu_data.cputype == CPU_34K) + return counters >> 1; +#endif + + return counters; +} + static inline void reset_counters(int counters) { switch (counters) { case 4: - write_c0_perfctrl3(0); - write_c0_perfcntr3(0); + w_c0_perfctrl3(0); + w_c0_perfcntr3(0); case 3: - write_c0_perfctrl2(0); - write_c0_perfcntr2(0); + w_c0_perfctrl2(0); + w_c0_perfcntr2(0); case 2: - write_c0_perfctrl1(0); - write_c0_perfcntr1(0); + w_c0_perfctrl1(0); + w_c0_perfcntr1(0); case 1: - write_c0_perfctrl0(0); - write_c0_perfcntr0(0); + w_c0_perfctrl0(0); + w_c0_perfcntr0(0); } } @@ -201,7 +267,6 @@ static int __init mipsxx_init(void) op_model_mipsxx_ops.cpu_type = "mips/25K"; break; -#ifndef CONFIG_SMP case CPU_34K: op_model_mipsxx_ops.cpu_type = "mips/34K"; break; @@ -209,7 +274,6 @@ static int __init mipsxx_init(void) case CPU_74K: op_model_mipsxx_ops.cpu_type = "mips/74K"; break; -#endif case CPU_5KC: op_model_mipsxx_ops.cpu_type = "mips/5K"; diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index 465778c..35d5927 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -23,7 +23,7 @@ obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o # # These are still pretty much in the old state, watch, go blind. # -obj-$(CONFIG_BASLER_EXCITE) = ops-titan.o pci-excite.o fixup-excite.o +obj-$(CONFIG_BASLER_EXCITE) += ops-titan.o pci-excite.o fixup-excite.o obj-$(CONFIG_DDB5477) += fixup-ddb5477.o pci-ddb5477.o ops-ddb5477.o obj-$(CONFIG_LASAT) += pci-lasat.o obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o diff --git a/arch/mips/pci/ops-tx4927.c b/arch/mips/pci/ops-tx4927.c index 7688b77..150419c 100644 --- a/arch/mips/pci/ops-tx4927.c +++ b/arch/mips/pci/ops-tx4927.c @@ -119,7 +119,7 @@ static int tx4927_pcibios_read_config(struct pci_bus *bus, unsigned int devfn, i switch (size) { case 1: - *val = *(volatile u8 *) ((ulong) & tx4927_pcicptr-> + *val = *(volatile u8 *) ((unsigned long) & tx4927_pcicptr-> g2pcfgdata | #ifdef __LITTLE_ENDIAN (where & 3)); @@ -128,7 +128,7 @@ static int tx4927_pcibios_read_config(struct pci_bus *bus, unsigned int devfn, i #endif break; case 2: - *val = *(volatile u16 *) ((ulong) & tx4927_pcicptr-> + *val = *(volatile u16 *) ((unsigned long) & tx4927_pcicptr-> g2pcfgdata | #ifdef __LITTLE_ENDIAN (where & 3)); @@ -168,7 +168,7 @@ static int tx4927_pcibios_write_config(struct pci_bus *bus, unsigned int devfn, switch (size) { case 1: - *(volatile u8 *) ((ulong) & tx4927_pcicptr-> + *(volatile u8 *) ((unsigned long) & tx4927_pcicptr-> g2pcfgdata | #ifdef __LITTLE_ENDIAN (where & 3)) = val; @@ -178,7 +178,7 @@ static int tx4927_pcibios_write_config(struct pci_bus *bus, unsigned int devfn, break; case 2: - *(volatile u16 *) ((ulong) & tx4927_pcicptr-> + *(volatile u16 *) ((unsigned long) & tx4927_pcicptr-> g2pcfgdata | #ifdef __LITTLE_ENDIAN (where & 3)) = val; diff --git a/arch/mips/pci/ops-tx4938.c b/arch/mips/pci/ops-tx4938.c index 0ff0834..4450070 100644 --- a/arch/mips/pci/ops-tx4938.c +++ b/arch/mips/pci/ops-tx4938.c @@ -106,7 +106,7 @@ static int tx4938_pcibios_read_config(struct pci_bus *bus, unsigned int devfn, switch (size) { case 1: - *val = *(volatile u8 *) ((ulong) & tx4938_pcicptr->g2pcfgdata | + *val = *(volatile u8 *) ((unsigned long) & tx4938_pcicptr->g2pcfgdata | #ifdef __BIG_ENDIAN ((where & 3) ^ 3)); #else @@ -114,7 +114,7 @@ static int tx4938_pcibios_read_config(struct pci_bus *bus, unsigned int devfn, #endif break; case 2: - *val = *(volatile u16 *) ((ulong) & tx4938_pcicptr->g2pcfgdata | + *val = *(volatile u16 *) ((unsigned long) & tx4938_pcicptr->g2pcfgdata | #ifdef __BIG_ENDIAN ((where & 3) ^ 2)); #else @@ -154,7 +154,7 @@ static int tx4938_pcibios_write_config(struct pci_bus *bus, unsigned int devfn, switch (size) { case 1: - *(volatile u8 *) ((ulong) & tx4938_pcicptr->g2pcfgdata | + *(volatile u8 *) ((unsigned long) & tx4938_pcicptr->g2pcfgdata | #ifdef __BIG_ENDIAN ((where & 3) ^ 3)) = val; #else @@ -162,7 +162,7 @@ static int tx4938_pcibios_write_config(struct pci_bus *bus, unsigned int devfn, #endif break; case 2: - *(volatile u16 *) ((ulong) & tx4938_pcicptr->g2pcfgdata | + *(volatile u16 *) ((unsigned long) & tx4938_pcicptr->g2pcfgdata | #ifdef __BIG_ENDIAN ((where & 0x3) ^ 0x2)) = val; #else diff --git a/arch/mips/sgi-ip27/Kconfig b/arch/mips/sgi-ip27/Kconfig index f14ef38..5e960ae 100644 --- a/arch/mips/sgi-ip27/Kconfig +++ b/arch/mips/sgi-ip27/Kconfig @@ -33,12 +33,13 @@ config MAPPED_KERNEL depends on SGI_IP27 help Change the way a Linux kernel is loaded into memory on a MIPS64 - machine. This is required in order to support text replication and + machine. This is required in order to support text replication on NUMA. If you need to understand it, read the source code. config REPLICATE_KTEXT bool "Kernel text replication support" depends on SGI_IP27 + select MAPPED_KERNEL help Say Y here to enable replicating the kernel text across multiple nodes in a NUMA cluster. This trades memory for speed. diff --git a/arch/mips/sgi-ip27/Makefile b/arch/mips/sgi-ip27/Makefile index 686ba14..a457263 100644 --- a/arch/mips/sgi-ip27/Makefile +++ b/arch/mips/sgi-ip27/Makefile @@ -2,11 +2,12 @@ # Makefile for the IP27 specific kernel interface routines under Linux. # -obj-y := ip27-berr.o ip27-console.o ip27-irq.o ip27-init.o \ - ip27-klconfig.o ip27-klnuma.o ip27-memory.o ip27-nmi.o ip27-reset.o \ - ip27-timer.o ip27-hubio.o ip27-xtalk.o +obj-y := ip27-berr.o ip27-irq.o ip27-init.o ip27-klconfig.o ip27-klnuma.o \ + ip27-memory.o ip27-nmi.o ip27-reset.o ip27-timer.o ip27-hubio.o \ + ip27-xtalk.o -obj-$(CONFIG_KGDB) += ip27-dbgio.o -obj-$(CONFIG_SMP) += ip27-smp.o +obj-$(CONFIG_EARLY_PRINTK) += ip27-console.o +obj-$(CONFIG_KGDB) += ip27-dbgio.o +obj-$(CONFIG_SMP) += ip27-smp.o EXTRA_AFLAGS := $(CFLAGS) diff --git a/arch/mips/sgi-ip27/ip27-console.c b/arch/mips/sgi-ip27/ip27-console.c index 3e1ac29..14211e3 100644 --- a/arch/mips/sgi-ip27/ip27-console.c +++ b/arch/mips/sgi-ip27/ip27-console.c @@ -46,33 +46,29 @@ void prom_putchar(char c) uart->iu_thr = c; } -char __init prom_getchar(void) +static void ioc3_console_write(struct console *con, const char *s, unsigned n) { - return 0; + while (n-- && *s) { + if (*s == '\n') + prom_putchar('\r'); + prom_putchar(*s); + s++; + } } -static void inline ioc3_console_probe(void) -{ - struct uart_port up; - - /* - * Register to interrupt zero because we share the interrupt with - * the serial driver which we don't properly support yet. - */ - memset(&up, 0, sizeof(up)); - up.membase = (unsigned char *) console_uart(); - up.irq = 0; - up.uartclk = IOC3_CLK; - up.regshift = 0; - up.iotype = UPIO_MEM; - up.flags = IOC3_FLAGS; - up.line = 0; +static struct console ioc3_console = { + .name = "ioc3", + .write = ioc3_console_write, + .flags = CON_PRINTBUFFER | CON_BOOT, + .index = -1 +}; - if (early_serial_setup(&up)) - printk(KERN_ERR "Early serial init of port 0 failed\n"); +__init void ip27_setup_console(void) +{ + register_console(&ioc3_console); } -__init void ip27_setup_console(void) +void __init disable_early_printk(void) { - ioc3_console_probe(); + unregister_console(&ioc3_console); } diff --git a/arch/mips/sibyte/Kconfig b/arch/mips/sibyte/Kconfig index 816aee7..ec7a2cf 100644 --- a/arch/mips/sibyte/Kconfig +++ b/arch/mips/sibyte/Kconfig @@ -3,6 +3,7 @@ config SIBYTE_SB1250 select HW_HAS_PCI select SIBYTE_HAS_LDT select SIBYTE_SB1xxx_SOC + select SYS_SUPPORTS_SMP config SIBYTE_BCM1120 bool @@ -30,11 +31,13 @@ config SIBYTE_BCM1x80 bool select HW_HAS_PCI select SIBYTE_SB1xxx_SOC + select SYS_SUPPORTS_SMP config SIBYTE_BCM1x55 bool select HW_HAS_PCI select SIBYTE_SB1xxx_SOC + select SYS_SUPPORTS_SMP config SIBYTE_SB1xxx_SOC bool |