diff options
Diffstat (limited to 'include/asm-sparc64')
| -rw-r--r-- | include/asm-sparc64/auxio.h | 2 | ||||
| -rw-r--r-- | include/asm-sparc64/floppy.h | 16 | ||||
| -rw-r--r-- | include/asm-sparc64/irq.h | 56 | ||||
| -rw-r--r-- | include/asm-sparc64/pbm.h | 3 | ||||
| -rw-r--r-- | include/asm-sparc64/pci.h | 19 | ||||
| -rw-r--r-- | include/asm-sparc64/rwsem.h | 3 | ||||
| -rw-r--r-- | include/asm-sparc64/signal.h | 15 | ||||
| -rw-r--r-- | include/asm-sparc64/spinlock.h | 29 | ||||
| -rw-r--r-- | include/asm-sparc64/spitfire.h | 1 |
9 files changed, 74 insertions, 70 deletions
diff --git a/include/asm-sparc64/auxio.h b/include/asm-sparc64/auxio.h index 5eb01dd..81a590a 100644 --- a/include/asm-sparc64/auxio.h +++ b/include/asm-sparc64/auxio.h @@ -75,6 +75,8 @@ #ifndef __ASSEMBLY__ +extern void __iomem *auxio_register; + #define AUXIO_LTE_ON 1 #define AUXIO_LTE_OFF 0 diff --git a/include/asm-sparc64/floppy.h b/include/asm-sparc64/floppy.h index e071b4b..49d49a2 100644 --- a/include/asm-sparc64/floppy.h +++ b/include/asm-sparc64/floppy.h @@ -159,7 +159,7 @@ static void sun_82077_fd_outb(unsigned char value, unsigned long port) * underruns. If non-zero, doing_pdma encodes the direction of * the transfer for debugging. 1=read 2=write */ -char *pdma_vaddr; +unsigned char *pdma_vaddr; unsigned long pdma_size; volatile int doing_pdma = 0; @@ -209,8 +209,7 @@ static void sun_fd_enable_dma(void) pdma_areasize = pdma_size; } -/* Our low-level entry point in arch/sparc/kernel/entry.S */ -extern irqreturn_t floppy_hardint(int irq, void *unused, struct pt_regs *regs); +extern irqreturn_t sparc_floppy_irq(int, void *, struct pt_regs *); static int sun_fd_request_irq(void) { @@ -220,8 +219,8 @@ static int sun_fd_request_irq(void) if(!once) { once = 1; - error = request_fast_irq(FLOPPY_IRQ, floppy_hardint, - SA_INTERRUPT, "floppy", NULL); + error = request_irq(FLOPPY_IRQ, sparc_floppy_irq, + SA_INTERRUPT, "floppy", NULL); return ((error == 0) ? 0 : -1); } @@ -615,7 +614,7 @@ static unsigned long __init sun_floppy_init(void) struct linux_ebus *ebus; struct linux_ebus_device *edev = NULL; unsigned long config = 0; - unsigned long auxio_reg; + void __iomem *auxio_reg; for_each_ebus(ebus) { for_each_ebusdev(edev, ebus) { @@ -642,7 +641,7 @@ static unsigned long __init sun_floppy_init(void) /* Make sure the high density bit is set, some systems * (most notably Ultra5/Ultra10) come up with it clear. */ - auxio_reg = edev->resource[2].start; + auxio_reg = (void __iomem *) edev->resource[2].start; writel(readl(auxio_reg)|0x2, auxio_reg); sun_pci_ebus_dev = ebus->self; @@ -650,7 +649,8 @@ static unsigned long __init sun_floppy_init(void) spin_lock_init(&sun_pci_fd_ebus_dma.lock); /* XXX ioremap */ - sun_pci_fd_ebus_dma.regs = edev->resource[1].start; + sun_pci_fd_ebus_dma.regs = (void __iomem *) + edev->resource[1].start; if (!sun_pci_fd_ebus_dma.regs) return 0; diff --git a/include/asm-sparc64/irq.h b/include/asm-sparc64/irq.h index 3aef0ca..8b70edc 100644 --- a/include/asm-sparc64/irq.h +++ b/include/asm-sparc64/irq.h @@ -16,10 +16,22 @@ #include <asm/pil.h> #include <asm/ptrace.h> +struct ino_bucket; + +#define MAX_IRQ_DESC_ACTION 4 + +struct irq_desc { + void (*pre_handler)(struct ino_bucket *, void *, void *); + void *pre_handler_arg1; + void *pre_handler_arg2; + u32 action_active_mask; + struct irqaction action[MAX_IRQ_DESC_ACTION]; +}; + /* You should not mess with this directly. That's the job of irq.c. * * If you make changes here, please update hand coded assembler of - * SBUS/floppy interrupt handler in entry.S -DaveM + * the vectored interrupt trap handler in entry.S -DaveM * * This is currently one DCACHE line, two buckets per L2 cache * line. Keep this in mind please. @@ -42,24 +54,11 @@ struct ino_bucket { /* Miscellaneous flags. */ /*0x06*/unsigned char flags; - /* This is used to deal with IBF_DMA_SYNC on - * Sabre systems. - */ -/*0x07*/unsigned char synctab_ent; - - /* Reference to handler for this IRQ. If this is - * non-NULL this means it is active and should be - * serviced. Else the pending member is set to one - * and later registry of the interrupt checks for - * this condition. - * - * Normally this is just an irq_action structure. - * But, on PCI, if multiple interrupt sources behind - * a bridge have multiple interrupt sources that share - * the same INO bucket, this points to an array of - * pointers to four IRQ action structures. - */ -/*0x08*/void *irq_info; + /* Currently unused. */ +/*0x07*/unsigned char __pad; + + /* Reference to IRQ descriptor for this bucket. */ +/*0x08*/struct irq_desc *irq_info; /* Sun5 Interrupt Clear Register. */ /*0x10*/unsigned long iclr; @@ -69,12 +68,6 @@ struct ino_bucket { }; -#ifdef CONFIG_PCI -extern unsigned long pci_dma_wsync; -extern unsigned long dma_sync_reg_table[256]; -extern unsigned char dma_sync_reg_table_entry; -#endif - /* IMAP/ICLR register defines */ #define IMAP_VALID 0x80000000 /* IRQ Enabled */ #define IMAP_TID_UPA 0x7c000000 /* UPA TargetID */ @@ -90,11 +83,9 @@ extern unsigned char dma_sync_reg_table_entry; #define ICLR_PENDING 0x00000003 /* Pending state */ /* Only 8-bits are available, be careful. -DaveM */ -#define IBF_DMA_SYNC 0x01 /* DMA synchronization behind PCI bridge needed. */ -#define IBF_PCI 0x02 /* Indicates PSYCHO/SABRE/SCHIZO PCI interrupt. */ -#define IBF_ACTIVE 0x04 /* This interrupt is active and has a handler. */ -#define IBF_MULTI 0x08 /* On PCI, indicates shared bucket. */ -#define IBF_INPROGRESS 0x10 /* IRQ is being serviced. */ +#define IBF_PCI 0x02 /* PSYCHO/SABRE/SCHIZO PCI interrupt. */ +#define IBF_ACTIVE 0x04 /* Interrupt is active and has a handler.*/ +#define IBF_INPROGRESS 0x10 /* IRQ is being serviced. */ #define NUM_IVECS (IMAP_INR + 1) extern struct ino_bucket ivector_table[NUM_IVECS]; @@ -122,11 +113,6 @@ extern void enable_irq(unsigned int); extern unsigned int build_irq(int pil, int inofixup, unsigned long iclr, unsigned long imap); extern unsigned int sbus_build_irq(void *sbus, unsigned int ino); -extern int request_fast_irq(unsigned int irq, - irqreturn_t (*handler)(int, void *, struct pt_regs *), - unsigned long flags, __const__ char *devname, - void *dev_id); - static __inline__ void set_softint(unsigned long bits) { __asm__ __volatile__("wr %0, 0x0, %%set_softint" diff --git a/include/asm-sparc64/pbm.h b/include/asm-sparc64/pbm.h index 4c15610..38bbbcc 100644 --- a/include/asm-sparc64/pbm.h +++ b/include/asm-sparc64/pbm.h @@ -145,6 +145,9 @@ struct pci_pbm_info { /* Physical address base of PBM registers. */ unsigned long pbm_regs; + /* Physical address of DMA sync register, if any. */ + unsigned long sync_reg; + /* Opaque 32-bit system bus Port ID. */ u32 portid; diff --git a/include/asm-sparc64/pci.h b/include/asm-sparc64/pci.h index 2a0c85c..84e41c1 100644 --- a/include/asm-sparc64/pci.h +++ b/include/asm-sparc64/pci.h @@ -220,6 +220,25 @@ static inline int pci_dma_mapping_error(dma_addr_t dma_addr) return (dma_addr == PCI_DMA_ERROR_CODE); } +#ifdef CONFIG_PCI +static inline void pci_dma_burst_advice(struct pci_dev *pdev, + enum pci_dma_burst_strategy *strat, + unsigned long *strategy_parameter) +{ + unsigned long cacheline_size; + u8 byte; + + pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte); + if (byte == 0) + cacheline_size = 1024; + else + cacheline_size = (int) byte * 4; + + *strat = PCI_DMA_BURST_BOUNDARY; + *strategy_parameter = cacheline_size; +} +#endif + /* Return the index of the PCI controller for device PDEV. */ extern int pci_domain_nr(struct pci_bus *bus); diff --git a/include/asm-sparc64/rwsem.h b/include/asm-sparc64/rwsem.h index bf2ae90..a1cc94f 100644 --- a/include/asm-sparc64/rwsem.h +++ b/include/asm-sparc64/rwsem.h @@ -55,8 +55,9 @@ static __inline__ int rwsem_atomic_update(int delta, struct rw_semaphore *sem) "add %%g1, %1, %%g7\n\t" "cas [%2], %%g1, %%g7\n\t" "cmp %%g1, %%g7\n\t" + "membar #StoreLoad | #StoreStore\n\t" "bne,pn %%icc, 1b\n\t" - " membar #StoreLoad | #StoreStore\n\t" + " nop\n\t" "mov %%g7, %0\n\t" : "=&r" (tmp) : "0" (tmp), "r" (sem) diff --git a/include/asm-sparc64/signal.h b/include/asm-sparc64/signal.h index becdf1b..e3059bb 100644 --- a/include/asm-sparc64/signal.h +++ b/include/asm-sparc64/signal.h @@ -162,21 +162,6 @@ struct sigstack { #define MINSIGSTKSZ 4096 #define SIGSTKSZ 16384 -#ifdef __KERNEL__ -/* - * DJHR - * SA_STATIC_ALLOC is used for the SPARC system to indicate that this - * interrupt handler's irq structure should be statically allocated - * by the request_irq routine. - * The alternative is that arch/sparc/kernel/irq.c has carnal knowledge - * of interrupt usage and that sucks. Also without a flag like this - * it may be possible for the free_irq routine to attempt to free - * statically allocated data.. which is NOT GOOD. - * - */ -#define SA_STATIC_ALLOC 0x80 -#endif - #include <asm-generic/signal.h> struct __new_sigaction { diff --git a/include/asm-sparc64/spinlock.h b/include/asm-sparc64/spinlock.h index db7581b..9cb93a5 100644 --- a/include/asm-sparc64/spinlock.h +++ b/include/asm-sparc64/spinlock.h @@ -52,12 +52,14 @@ static inline void _raw_spin_lock(spinlock_t *lock) __asm__ __volatile__( "1: ldstub [%1], %0\n" +" membar #StoreLoad | #StoreStore\n" " brnz,pn %0, 2f\n" -" membar #StoreLoad | #StoreStore\n" +" nop\n" " .subsection 2\n" "2: ldub [%1], %0\n" +" membar #LoadLoad\n" " brnz,pt %0, 2b\n" -" membar #LoadLoad\n" +" nop\n" " ba,a,pt %%xcc, 1b\n" " .previous" : "=&r" (tmp) @@ -95,16 +97,18 @@ static inline void _raw_spin_lock_flags(spinlock_t *lock, unsigned long flags) __asm__ __volatile__( "1: ldstub [%2], %0\n" -" brnz,pn %0, 2f\n" " membar #StoreLoad | #StoreStore\n" +" brnz,pn %0, 2f\n" +" nop\n" " .subsection 2\n" "2: rdpr %%pil, %1\n" " wrpr %3, %%pil\n" "3: ldub [%2], %0\n" -" brnz,pt %0, 3b\n" " membar #LoadLoad\n" +" brnz,pt %0, 3b\n" +" nop\n" " ba,pt %%xcc, 1b\n" -" wrpr %1, %%pil\n" +" wrpr %1, %%pil\n" " .previous" : "=&r" (tmp1), "=&r" (tmp2) : "r"(lock), "r"(flags) @@ -162,12 +166,14 @@ static void inline __read_lock(rwlock_t *lock) "4: add %0, 1, %1\n" " cas [%2], %0, %1\n" " cmp %0, %1\n" +" membar #StoreLoad | #StoreStore\n" " bne,pn %%icc, 1b\n" -" membar #StoreLoad | #StoreStore\n" +" nop\n" " .subsection 2\n" "2: ldsw [%2], %0\n" +" membar #LoadLoad\n" " brlz,pt %0, 2b\n" -" membar #LoadLoad\n" +" nop\n" " ba,a,pt %%xcc, 4b\n" " .previous" : "=&r" (tmp1), "=&r" (tmp2) @@ -204,12 +210,14 @@ static void inline __write_lock(rwlock_t *lock) "4: or %0, %3, %1\n" " cas [%2], %0, %1\n" " cmp %0, %1\n" +" membar #StoreLoad | #StoreStore\n" " bne,pn %%icc, 1b\n" -" membar #StoreLoad | #StoreStore\n" +" nop\n" " .subsection 2\n" "2: lduw [%2], %0\n" +" membar #LoadLoad\n" " brnz,pt %0, 2b\n" -" membar #LoadLoad\n" +" nop\n" " ba,a,pt %%xcc, 4b\n" " .previous" : "=&r" (tmp1), "=&r" (tmp2) @@ -240,8 +248,9 @@ static int inline __write_trylock(rwlock_t *lock) " or %0, %4, %1\n" " cas [%3], %0, %1\n" " cmp %0, %1\n" +" membar #StoreLoad | #StoreStore\n" " bne,pn %%icc, 1b\n" -" membar #StoreLoad | #StoreStore\n" +" nop\n" " mov 1, %2\n" "2:" : "=&r" (tmp1), "=&r" (tmp2), "=&r" (result) diff --git a/include/asm-sparc64/spitfire.h b/include/asm-sparc64/spitfire.h index 9d7613e..1aa9327 100644 --- a/include/asm-sparc64/spitfire.h +++ b/include/asm-sparc64/spitfire.h @@ -111,7 +111,6 @@ static __inline__ void spitfire_put_dcache_tag(unsigned long addr, unsigned long "membar #Sync" : /* No outputs */ : "r" (tag), "r" (addr), "i" (ASI_DCACHE_TAG)); - __asm__ __volatile__ ("membar #Sync" : : : "memory"); } /* The instruction cache lines are flushed with this, but note that |